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            <description>&lt;div&gt;&lt;strong&gt;Rev 155 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Improved debug trace quality, for finding bugs after the fact.&lt;/div&gt;~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp&lt;br /&gt;</description>
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            <description>&lt;div&gt;&lt;strong&gt;Rev 154 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Added timing checks on the busy and valid signals: either ...&lt;/div&gt;~ /zipcpu/trunk/bench/cpp/div_tb.cpp&lt;br /&gt;</description>
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            <pubDate>Wed, 15 Jun 2016 00:17:14 +0100</pubDate>
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            <description>&lt;div&gt;&lt;strong&gt;Rev 152 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Updated to match the new/updated multiply instructions.  Of course, ...&lt;/div&gt;~ /zipcpu/trunk/bench/asm/zipdhry.S&lt;br /&gt;</description>
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            <pubDate>Fri, 13 May 2016 02:05:54 +0100</pubDate>
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            <title>Minor formatting change.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=151</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 151 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Minor formatting change.&lt;/div&gt;~ /zipcpu/trunk/bench/asm/lfsr.S&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Fri, 13 May 2016 02:01:55 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=151</guid>
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            <title>Minor changes.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=150</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 150 - dgisselq&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Minor changes.&lt;/div&gt;~ /zipcpu/trunk/bench/asm/helloworld.S&lt;br /&gt;~ /zipcpu/trunk/bench/asm/lodsto.S&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Fri, 13 May 2016 02:00:56 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=150</guid>
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            <title>Updated the Makefile documentation and the all target.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=149</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 149 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Updated the Makefile documentation and the all target.&lt;/div&gt;~ /zipcpu/trunk/bench/cpp/Makefile&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Fri, 13 May 2016 01:56:01 +0100</pubDate>
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            <title>Minor changes to get LONG_MPY working, and adjust the documentation.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=148</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 148 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Minor changes to get LONG_MPY working, and adjust the documentation.&lt;/div&gt;~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Fri, 13 May 2016 01:55:23 +0100</pubDate>
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            <title>Cleans up div_tb a bit, causing it to write SUCCESS ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=147</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 147 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Cleans up div_tb a bit, causing it to write SUCCESS ...&lt;/div&gt;~ /zipcpu/trunk/bench/cpp/div_tb.cpp&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Fri, 13 May 2016 01:54:06 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=147</guid>
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            <title>Minor changes, but fixes build of zippy_tb.cpp.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=140</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 140 - dgisselq&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Minor changes, but fixes build of zippy_tb.cpp.&lt;/div&gt;~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp&lt;br /&gt;~ /zipcpu/trunk/rtl/core/idecode.v&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Mon, 09 May 2016 12:19:09 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=140</guid>
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            <title>Working updates, to keep this up to date with the ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=134</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 134 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Working updates, to keep this up to date with the ...&lt;/div&gt;~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Fri, 22 Apr 2016 00:21:03 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=134</guid>
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            <title>Fixed some nasty early branching bugs.  Adjusted the Makefile ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=105</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 105 - dgisselq&lt;/strong&gt; (7 file(s) modified)&lt;/div&gt;&lt;div&gt;Fixed some nasty early branching bugs.  Adjusted the Makefile ...&lt;/div&gt;~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp&lt;br /&gt;~ /zipcpu/trunk/rtl/core/idecode.v&lt;br /&gt;~ /zipcpu/trunk/rtl/core/idecode_deprecated.v&lt;br /&gt;~ /zipcpu/trunk/rtl/core/zipcpu.v&lt;br /&gt;~ /zipcpu/trunk/rtl/Makefile&lt;br /&gt;~ /zipcpu/trunk/rtl/zipbones.v&lt;br /&gt;~ /zipcpu/trunk/sw/zasm/test.S&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Wed, 09 Mar 2016 15:26:16 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=105</guid>
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            <title>Adjusted the operator input line to reflect actual logic inputs, ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=87</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 87 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Adjusted the operator input line to reflect actual logic inputs, ...&lt;/div&gt;~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Sat, 02 Jan 2016 23:56:30 +0100</pubDate>
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            <title>Removed the requirement to have the dev.scope.cpu hardware defined outside
of ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=86</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 86 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Removed the requirement to have the dev.scope.cpu hardware defined outside&lt;br /&gt;
of ...&lt;/div&gt;~ /zipcpu/trunk/bench/asm/zipdhry.S&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Sat, 02 Jan 2016 23:55:01 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=86</guid>
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            <title>First check-in: the test bench for the divide instruction.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=77</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 77 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;First check-in: the test bench for the divide instruction.&lt;/div&gt;+ /zipcpu/trunk/bench/cpp/div_tb.cpp&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Mon, 28 Dec 2015 20:53:32 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=77</guid>
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            <title>The biggest change here was to zippy_tb, to make it ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=76</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 76 - dgisselq&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;The biggest change here was to zippy_tb, to make it ...&lt;/div&gt;~ /zipcpu/trunk/bench/cpp/Makefile&lt;br /&gt;~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Mon, 28 Dec 2015 20:50:30 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=76</guid>
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        <item>
            <title>Modified for VLIW instructions.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=75</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 75 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Modified for VLIW instructions.&lt;/div&gt;~ /zipcpu/trunk/bench/cpp/pdump.cpp&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Mon, 28 Dec 2015 20:49:16 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=75</guid>
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        <item>
            <title>Added a bunch of debugging code to the Dhrystone benchmark ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=74</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 74 - dgisselq&lt;/strong&gt; (4 file(s) modified)&lt;/div&gt;&lt;div&gt;Added a bunch of debugging code to the Dhrystone benchmark ...&lt;/div&gt;~ /zipcpu/trunk/bench/asm/Makefile&lt;br /&gt;+ /zipcpu/trunk/bench/asm/nullpc.s&lt;br /&gt;+ /zipcpu/trunk/bench/asm/poptest.s&lt;br /&gt;~ /zipcpu/trunk/bench/asm/zipdhry.S&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Mon, 28 Dec 2015 20:48:36 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=74</guid>
        </item>
        <item>
            <title>This implements the &amp;quot;new Instruction Set&amp;quot; architecture for the Zip ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=69</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 69 - dgisselq&lt;/strong&gt; (85 file(s) modified)&lt;/div&gt;&lt;div&gt;This implements the &amp;quot;new Instruction Set&amp;quot; architecture for the Zip ...&lt;/div&gt;~ /zipcpu/trunk/bench/asm/helloworld.S&lt;br /&gt;~ /zipcpu/trunk/bench/asm/ivec.S&lt;br /&gt;~ /zipcpu/trunk/bench/asm/lodsto.S&lt;br /&gt;~ /zipcpu/trunk/bench/asm/Makefile&lt;br /&gt;~ /zipcpu/trunk/bench/asm/pcpc.S&lt;br /&gt;~ /zipcpu/trunk/bench/asm/testdiv.S&lt;br /&gt;~ /zipcpu/trunk/bench/asm/wdt.S&lt;br /&gt;~ /zipcpu/trunk/bench/asm/zipdhry.S&lt;br /&gt;~ /zipcpu/trunk/bench/cpp/Makefile&lt;br /&gt;~ /zipcpu/trunk/bench/cpp/memsim.cpp&lt;br /&gt;~ /zipcpu/trunk/bench/cpp/memsim.h&lt;br /&gt;~ /zipcpu/trunk/bench/cpp/pdump.cpp&lt;br /&gt;~ /zipcpu/trunk/bench/cpp/testb.h&lt;br /&gt;~ /zipcpu/trunk/bench/cpp/twoc.cpp&lt;br /&gt;~ /zipcpu/trunk/bench/cpp/twoc.h&lt;br /&gt;~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp&lt;br /&gt;~ /zipcpu/trunk/doc/gfx/bc.eps&lt;br /&gt;~ /zipcpu/trunk/doc/gfx/bra.eps&lt;br /&gt;~ /zipcpu/trunk/doc/gfx/cpu.dia&lt;br /&gt;~ /zipcpu/trunk/doc/gfx/cpu.eps&lt;br /&gt;~ /zipcpu/trunk/doc/gfx/cpu.png&lt;br /&gt;~ /zipcpu/trunk/doc/gfx/memrd.eps&lt;br /&gt;~ /zipcpu/trunk/doc/gfx/memwr.eps&lt;br /&gt;~ /zipcpu/trunk/doc/gfx/regset.png&lt;br /&gt;~ /zipcpu/trunk/doc/gfx/system.dia&lt;br /&gt;~ /zipcpu/trunk/doc/gfx/system.eps&lt;br /&gt;~ /zipcpu/trunk/doc/gfx/system.png&lt;br /&gt;~ /zipcpu/trunk/doc/gfx/zipbones.dia&lt;br /&gt;~ /zipcpu/trunk/doc/gfx/zipbones.png&lt;br /&gt;~ /zipcpu/trunk/doc/iset.html&lt;br /&gt;~ /zipcpu/trunk/doc/Makefile&lt;br /&gt;~ /zipcpu/trunk/doc/spec.pdf&lt;br /&gt;~ /zipcpu/trunk/doc/src/spec.tex&lt;br /&gt;~ /zipcpu/trunk/Makefile&lt;br /&gt;~ /zipcpu/trunk/rtl/aux/busdelay.v&lt;br /&gt;~ /zipcpu/trunk/rtl/aux/wbarbiter.v&lt;br /&gt;~ /zipcpu/trunk/rtl/aux/wbdblpriarb.v&lt;br /&gt;~ /zipcpu/trunk/rtl/aux/wbpriarbiter.v&lt;br /&gt;~ /zipcpu/trunk/rtl/core/cpuops.v&lt;br /&gt;+ /zipcpu/trunk/rtl/core/cpuops_deprecated.v&lt;br /&gt;+ /zipcpu/trunk/rtl/core/div.v&lt;br /&gt;+ /zipcpu/trunk/rtl/core/idecode.v&lt;br /&gt;+ /zipcpu/trunk/rtl/core/idecode_deprecated.v&lt;br /&gt;~ /zipcpu/trunk/rtl/core/memops.v&lt;br /&gt;+ /zipcpu/trunk/rtl/core/pfcache.v&lt;br /&gt;~ /zipcpu/trunk/rtl/core/pipefetch.v&lt;br /&gt;~ /zipcpu/trunk/rtl/core/pipemem.v&lt;br /&gt;~ /zipcpu/trunk/rtl/core/prefetch.v&lt;br /&gt;~ /zipcpu/trunk/rtl/core/zipcpu.v&lt;br /&gt;~ /zipcpu/trunk/rtl/cpudefs.v&lt;br /&gt;~ /zipcpu/trunk/rtl/Makefile&lt;br /&gt;~ /zipcpu/trunk/rtl/peripherals/flashcache.v&lt;br /&gt;~ /zipcpu/trunk/rtl/peripherals/icontrol.v&lt;br /&gt;~ /zipcpu/trunk/rtl/peripherals/wbdmac.v&lt;br /&gt;+ /zipcpu/trunk/rtl/peripherals/wbwatchdog.v&lt;br /&gt;~ /zipcpu/trunk/rtl/peripherals/zipcounter.v&lt;br /&gt;~ /zipcpu/trunk/rtl/peripherals/zipjiffies.v&lt;br /&gt;~ /zipcpu/trunk/rtl/peripherals/ziptimer.v&lt;br /&gt;~ /zipcpu/trunk/rtl/peripherals/ziptrap.v&lt;br /&gt;~ /zipcpu/trunk/rtl/zipbones.v&lt;br /&gt;~ /zipcpu/trunk/rtl/zipsystem.v&lt;br /&gt;~ /zipcpu/trunk/sw/lib/divs.S&lt;br /&gt;~ /zipcpu/trunk/sw/lib/divu.S&lt;br /&gt;~ /zipcpu/trunk/sw/lib/mpy32s.S&lt;br /&gt;~ /zipcpu/trunk/sw/lib/mpy32u.S&lt;br /&gt;~ /zipcpu/trunk/sw/zasm/asmdata.cpp&lt;br /&gt;~ /zipcpu/trunk/sw/zasm/asmdata.h&lt;br /&gt;~ /zipcpu/trunk/sw/zasm/Makefile&lt;br /&gt;~ /zipcpu/trunk/sw/zasm/optest.cpp&lt;br /&gt;~ /zipcpu/trunk/sw/zasm/sys.i&lt;br /&gt;~ /zipcpu/trunk/sw/zasm/test.S&lt;br /&gt;~ /zipcpu/trunk/sw/zasm/twoc.cpp&lt;br /&gt;~ /zipcpu/trunk/sw/zasm/twoc.h&lt;br /&gt;~ /zipcpu/trunk/sw/zasm/zasm.l&lt;br /&gt;~ /zipcpu/trunk/sw/zasm/zasm.y&lt;br /&gt;~ /zipcpu/trunk/sw/zasm/zdump.cpp&lt;br /&gt;~ /zipcpu/trunk/sw/zasm/zopcodes.cpp&lt;br /&gt;~ /zipcpu/trunk/sw/zasm/zopcodes.h&lt;br /&gt;~ /zipcpu/trunk/sw/zasm/zparser.cpp&lt;br /&gt;~ /zipcpu/trunk/sw/zasm/zparser.h&lt;br /&gt;~ /zipcpu/trunk/sw/zasm/zpp.l&lt;br /&gt;~ /zipcpu/trunk/sw/zipdbg/devbus.h&lt;br /&gt;~ /zipcpu/trunk/sw/zipdbg/regdefs.h&lt;br /&gt;~ /zipcpu/trunk/sw/zipdbg/zipdbg.cpp&lt;br /&gt;+ /zipcpu/trunk/zip.vim&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Tue, 22 Dec 2015 16:06:51 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=69</guid>
        </item>
        <item>
            <title>Added a rudimentary profiling support to the simulator.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=58</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 58 - dgisselq&lt;/strong&gt; (3 file(s) modified)&lt;/div&gt;&lt;div&gt;Added a rudimentary profiling support to the simulator.&lt;/div&gt;~ /zipcpu/trunk/bench/cpp/Makefile&lt;br /&gt;+ /zipcpu/trunk/bench/cpp/pdump.cpp&lt;br /&gt;~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Thu, 22 Oct 2015 15:26:48 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=58</guid>
        </item>
        <item>
            <title>Some bug fixes to the dhrystone benchmark, and some compile ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=57</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 57 - dgisselq&lt;/strong&gt; (3 file(s) modified)&lt;/div&gt;&lt;div&gt;Some bug fixes to the dhrystone benchmark, and some compile ...&lt;/div&gt;~ /zipcpu/trunk/bench/asm/Makefile&lt;br /&gt;~ /zipcpu/trunk/bench/asm/zipdhry.S&lt;br /&gt;~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Mon, 12 Oct 2015 13:30:15 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=57</guid>
        </item>
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