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zipcpu WebSVN RSS feed - zipcpu https://opencores.org/websvn//websvn/listing?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F& Fri, 19 Aug 2022 10:25:19 +0100 FeedCreator 1.7.2 Now supports building a simulator that can load ELF files, ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=159 <div><strong>Rev 159 - dgisselq</strong> (1 file(s) modified)</div><div>Now supports building a simulator that can load ELF files, ...</div>~ /zipcpu/trunk/bench/cpp/Makefile<br /> dgisselq Wed, 15 Jun 2016 00:27:23 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=159 Improved debug trace quality, for finding bugs after the fact. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=155 <div><strong>Rev 155 - dgisselq</strong> (1 file(s) modified)</div><div>Improved debug trace quality, for finding bugs after the fact.</div>~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br /> dgisselq Wed, 15 Jun 2016 00:19:12 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=155 Added timing checks on the busy and valid signals: either ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=154 <div><strong>Rev 154 - dgisselq</strong> (1 file(s) modified)</div><div>Added timing checks on the busy and valid signals: either ...</div>~ /zipcpu/trunk/bench/cpp/div_tb.cpp<br /> dgisselq Wed, 15 Jun 2016 00:17:14 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=154 Updated to match the new/updated multiply instructions. Of course, ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=152 <div><strong>Rev 152 - dgisselq</strong> (1 file(s) modified)</div><div>Updated to match the new/updated multiply instructions. Of course, ...</div>~ /zipcpu/trunk/bench/asm/zipdhry.S<br /> dgisselq Fri, 13 May 2016 02:05:54 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=152 Minor formatting change. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=151 <div><strong>Rev 151 - dgisselq</strong> (1 file(s) modified)</div><div>Minor formatting change.</div>~ /zipcpu/trunk/bench/asm/lfsr.S<br /> dgisselq Fri, 13 May 2016 02:01:55 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=151 Minor changes. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=150 <div><strong>Rev 150 - dgisselq</strong> (2 file(s) modified)</div><div>Minor changes.</div>~ /zipcpu/trunk/bench/asm/helloworld.S<br />~ /zipcpu/trunk/bench/asm/lodsto.S<br /> dgisselq Fri, 13 May 2016 02:00:56 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=150 Updated the Makefile documentation and the all target. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=149 <div><strong>Rev 149 - dgisselq</strong> (1 file(s) modified)</div><div>Updated the Makefile documentation and the all target.</div>~ /zipcpu/trunk/bench/cpp/Makefile<br /> dgisselq Fri, 13 May 2016 01:56:01 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=149 Minor changes to get LONG_MPY working, and adjust the documentation. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=148 <div><strong>Rev 148 - dgisselq</strong> (1 file(s) modified)</div><div>Minor changes to get LONG_MPY working, and adjust the documentation.</div>~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br /> dgisselq Fri, 13 May 2016 01:55:23 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=148 Cleans up div_tb a bit, causing it to write SUCCESS ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=147 <div><strong>Rev 147 - dgisselq</strong> (1 file(s) modified)</div><div>Cleans up div_tb a bit, causing it to write SUCCESS ...</div>~ /zipcpu/trunk/bench/cpp/div_tb.cpp<br /> dgisselq Fri, 13 May 2016 01:54:06 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=147 Minor changes, but fixes build of zippy_tb.cpp. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=140 <div><strong>Rev 140 - dgisselq</strong> (2 file(s) modified)</div><div>Minor changes, but fixes build of zippy_tb.cpp.</div>~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br />~ /zipcpu/trunk/rtl/core/idecode.v<br /> dgisselq Mon, 09 May 2016 12:19:09 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=140 Working updates, to keep this up to date with the ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=134 <div><strong>Rev 134 - dgisselq</strong> (1 file(s) modified)</div><div>Working updates, to keep this up to date with the ...</div>~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br /> dgisselq Fri, 22 Apr 2016 00:21:03 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=134 Fixed some nasty early branching bugs. Adjusted the Makefile ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=105 <div><strong>Rev 105 - dgisselq</strong> (7 file(s) modified)</div><div>Fixed some nasty early branching bugs. Adjusted the Makefile ...</div>~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br />~ /zipcpu/trunk/rtl/core/idecode.v<br />~ /zipcpu/trunk/rtl/core/idecode_deprecated.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/Makefile<br />~ /zipcpu/trunk/rtl/zipbones.v<br />~ /zipcpu/trunk/sw/zasm/test.S<br /> dgisselq Wed, 09 Mar 2016 15:26:16 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=105 Adjusted the operator input line to reflect actual logic inputs, ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=87 <div><strong>Rev 87 - dgisselq</strong> (1 file(s) modified)</div><div>Adjusted the operator input line to reflect actual logic inputs, ...</div>~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br /> dgisselq Sat, 02 Jan 2016 23:56:30 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=87 Removed the requirement to have the dev.scope.cpu hardware defined outside of ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=86 <div><strong>Rev 86 - dgisselq</strong> (1 file(s) modified)</div><div>Removed the requirement to have the dev.scope.cpu hardware defined outside<br /> of ...</div>~ /zipcpu/trunk/bench/asm/zipdhry.S<br /> dgisselq Sat, 02 Jan 2016 23:55:01 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=86 First check-in: the test bench for the divide instruction. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=77 <div><strong>Rev 77 - dgisselq</strong> (1 file(s) modified)</div><div>First check-in: the test bench for the divide instruction.</div>+ /zipcpu/trunk/bench/cpp/div_tb.cpp<br /> dgisselq Mon, 28 Dec 2015 20:53:32 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=77 The biggest change here was to zippy_tb, to make it ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=76 <div><strong>Rev 76 - dgisselq</strong> (2 file(s) modified)</div><div>The biggest change here was to zippy_tb, to make it ...</div>~ /zipcpu/trunk/bench/cpp/Makefile<br />~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br /> dgisselq Mon, 28 Dec 2015 20:50:30 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=76 Modified for VLIW instructions. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=75 <div><strong>Rev 75 - dgisselq</strong> (1 file(s) modified)</div><div>Modified for VLIW instructions.</div>~ /zipcpu/trunk/bench/cpp/pdump.cpp<br /> dgisselq Mon, 28 Dec 2015 20:49:16 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=75 Added a bunch of debugging code to the Dhrystone benchmark ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=74 <div><strong>Rev 74 - dgisselq</strong> (4 file(s) modified)</div><div>Added a bunch of debugging code to the Dhrystone benchmark ...</div>~ /zipcpu/trunk/bench/asm/Makefile<br />+ /zipcpu/trunk/bench/asm/nullpc.s<br />+ /zipcpu/trunk/bench/asm/poptest.s<br />~ /zipcpu/trunk/bench/asm/zipdhry.S<br /> dgisselq Mon, 28 Dec 2015 20:48:36 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=74 This implements the &quot;new Instruction Set&quot; architecture for the Zip ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=69 <div><strong>Rev 69 - dgisselq</strong> (85 file(s) modified)</div><div>This implements the &quot;new Instruction Set&quot; architecture for the Zip ...</div>~ /zipcpu/trunk/bench/asm/helloworld.S<br />~ /zipcpu/trunk/bench/asm/ivec.S<br />~ /zipcpu/trunk/bench/asm/lodsto.S<br />~ /zipcpu/trunk/bench/asm/Makefile<br />~ /zipcpu/trunk/bench/asm/pcpc.S<br />~ /zipcpu/trunk/bench/asm/testdiv.S<br />~ /zipcpu/trunk/bench/asm/wdt.S<br />~ /zipcpu/trunk/bench/asm/zipdhry.S<br />~ /zipcpu/trunk/bench/cpp/Makefile<br />~ /zipcpu/trunk/bench/cpp/memsim.cpp<br />~ /zipcpu/trunk/bench/cpp/memsim.h<br />~ /zipcpu/trunk/bench/cpp/pdump.cpp<br />~ /zipcpu/trunk/bench/cpp/testb.h<br />~ /zipcpu/trunk/bench/cpp/twoc.cpp<br />~ /zipcpu/trunk/bench/cpp/twoc.h<br />~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br />~ /zipcpu/trunk/doc/gfx/bc.eps<br />~ /zipcpu/trunk/doc/gfx/bra.eps<br />~ /zipcpu/trunk/doc/gfx/cpu.dia<br />~ /zipcpu/trunk/doc/gfx/cpu.eps<br />~ /zipcpu/trunk/doc/gfx/cpu.png<br />~ /zipcpu/trunk/doc/gfx/memrd.eps<br />~ /zipcpu/trunk/doc/gfx/memwr.eps<br />~ /zipcpu/trunk/doc/gfx/regset.png<br />~ /zipcpu/trunk/doc/gfx/system.dia<br />~ /zipcpu/trunk/doc/gfx/system.eps<br />~ /zipcpu/trunk/doc/gfx/system.png<br />~ /zipcpu/trunk/doc/gfx/zipbones.dia<br />~ /zipcpu/trunk/doc/gfx/zipbones.png<br />~ /zipcpu/trunk/doc/iset.html<br />~ /zipcpu/trunk/doc/Makefile<br />~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br />~ /zipcpu/trunk/Makefile<br />~ /zipcpu/trunk/rtl/aux/busdelay.v<br />~ /zipcpu/trunk/rtl/aux/wbarbiter.v<br />~ /zipcpu/trunk/rtl/aux/wbdblpriarb.v<br />~ /zipcpu/trunk/rtl/aux/wbpriarbiter.v<br />~ /zipcpu/trunk/rtl/core/cpuops.v<br />+ /zipcpu/trunk/rtl/core/cpuops_deprecated.v<br />+ /zipcpu/trunk/rtl/core/div.v<br />+ /zipcpu/trunk/rtl/core/idecode.v<br />+ /zipcpu/trunk/rtl/core/idecode_deprecated.v<br />~ /zipcpu/trunk/rtl/core/memops.v<br />+ /zipcpu/trunk/rtl/core/pfcache.v<br />~ /zipcpu/trunk/rtl/core/pipefetch.v<br />~ /zipcpu/trunk/rtl/core/pipemem.v<br />~ /zipcpu/trunk/rtl/core/prefetch.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/cpudefs.v<br />~ /zipcpu/trunk/rtl/Makefile<br />~ /zipcpu/trunk/rtl/peripherals/flashcache.v<br />~ /zipcpu/trunk/rtl/peripherals/icontrol.v<br />~ /zipcpu/trunk/rtl/peripherals/wbdmac.v<br />+ /zipcpu/trunk/rtl/peripherals/wbwatchdog.v<br />~ /zipcpu/trunk/rtl/peripherals/zipcounter.v<br />~ /zipcpu/trunk/rtl/peripherals/zipjiffies.v<br />~ /zipcpu/trunk/rtl/peripherals/ziptimer.v<br />~ /zipcpu/trunk/rtl/peripherals/ziptrap.v<br />~ /zipcpu/trunk/rtl/zipbones.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br />~ /zipcpu/trunk/sw/lib/divs.S<br />~ /zipcpu/trunk/sw/lib/divu.S<br />~ /zipcpu/trunk/sw/lib/mpy32s.S<br />~ /zipcpu/trunk/sw/lib/mpy32u.S<br />~ /zipcpu/trunk/sw/zasm/asmdata.cpp<br />~ /zipcpu/trunk/sw/zasm/asmdata.h<br />~ /zipcpu/trunk/sw/zasm/Makefile<br />~ /zipcpu/trunk/sw/zasm/optest.cpp<br />~ /zipcpu/trunk/sw/zasm/sys.i<br />~ /zipcpu/trunk/sw/zasm/test.S<br />~ /zipcpu/trunk/sw/zasm/twoc.cpp<br />~ /zipcpu/trunk/sw/zasm/twoc.h<br />~ /zipcpu/trunk/sw/zasm/zasm.l<br />~ /zipcpu/trunk/sw/zasm/zasm.y<br />~ /zipcpu/trunk/sw/zasm/zdump.cpp<br />~ /zipcpu/trunk/sw/zasm/zopcodes.cpp<br />~ /zipcpu/trunk/sw/zasm/zopcodes.h<br />~ /zipcpu/trunk/sw/zasm/zparser.cpp<br />~ /zipcpu/trunk/sw/zasm/zparser.h<br />~ /zipcpu/trunk/sw/zasm/zpp.l<br />~ /zipcpu/trunk/sw/zipdbg/devbus.h<br />~ /zipcpu/trunk/sw/zipdbg/regdefs.h<br />~ /zipcpu/trunk/sw/zipdbg/zipdbg.cpp<br />+ /zipcpu/trunk/zip.vim<br /> dgisselq Tue, 22 Dec 2015 16:06:51 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=69 Added a rudimentary profiling support to the simulator. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=58 <div><strong>Rev 58 - dgisselq</strong> (3 file(s) modified)</div><div>Added a rudimentary profiling support to the simulator.</div>~ /zipcpu/trunk/bench/cpp/Makefile<br />+ /zipcpu/trunk/bench/cpp/pdump.cpp<br />~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br /> dgisselq Thu, 22 Oct 2015 15:26:48 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=58
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