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            <description>&lt;div&gt;&lt;strong&gt;Rev 187 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Updated to match changed register definitions within the core.&lt;/div&gt;~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp&lt;br /&gt;</description>
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            <description>&lt;div&gt;&lt;strong&gt;Rev 186 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Now allows profile dumping for ELF executables.&lt;/div&gt;~ /zipcpu/trunk/bench/cpp/pdump.cpp&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Thu, 15 Sep 2016 20:31:19 +0100</pubDate>
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            <description>&lt;div&gt;&lt;strong&gt;Rev 185 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Now includes the proper flags for building with ELF executable ...&lt;/div&gt;~ /zipcpu/trunk/bench/cpp/Makefile&lt;br /&gt;</description>
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            <pubDate>Thu, 15 Sep 2016 20:30:29 +0100</pubDate>
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            <description>&lt;div&gt;&lt;strong&gt;Rev 172 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Added a test to see if the compiler properly handles ...&lt;/div&gt;~ /zipcpu/trunk/bench/asm/cputest.c&lt;br /&gt;</description>
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            <pubDate>Thu, 15 Sep 2016 20:02:35 +0100</pubDate>
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            <title>An updated version of the intensive CPU test.  This ...</title>
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            <description>&lt;div&gt;&lt;strong&gt;Rev 168 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;An updated version of the intensive CPU test.  This ...&lt;/div&gt;+ /zipcpu/trunk/bench/asm/cputest.c&lt;br /&gt;</description>
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            <pubDate>Sat, 16 Jul 2016 20:26:36 +0100</pubDate>
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            <description>&lt;div&gt;&lt;strong&gt;Rev 159 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Now supports building a simulator that can load ELF files, ...&lt;/div&gt;~ /zipcpu/trunk/bench/cpp/Makefile&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Wed, 15 Jun 2016 00:27:23 +0100</pubDate>
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            <title>Improved debug trace quality, for finding bugs after the fact.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=155</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 155 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Improved debug trace quality, for finding bugs after the fact.&lt;/div&gt;~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Wed, 15 Jun 2016 00:19:12 +0100</pubDate>
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            <title>Added timing checks on the busy and valid signals: either ...</title>
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            <description>&lt;div&gt;&lt;strong&gt;Rev 154 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Added timing checks on the busy and valid signals: either ...&lt;/div&gt;~ /zipcpu/trunk/bench/cpp/div_tb.cpp&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Wed, 15 Jun 2016 00:17:14 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=154</guid>
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            <title>Updated to match the new/updated multiply instructions.  Of course, ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=152</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 152 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Updated to match the new/updated multiply instructions.  Of course, ...&lt;/div&gt;~ /zipcpu/trunk/bench/asm/zipdhry.S&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Fri, 13 May 2016 02:05:54 +0100</pubDate>
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            <title>Minor formatting change.</title>
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            <description>&lt;div&gt;&lt;strong&gt;Rev 151 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Minor formatting change.&lt;/div&gt;~ /zipcpu/trunk/bench/asm/lfsr.S&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Fri, 13 May 2016 02:01:55 +0100</pubDate>
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            <title>Minor changes.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=150</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 150 - dgisselq&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Minor changes.&lt;/div&gt;~ /zipcpu/trunk/bench/asm/helloworld.S&lt;br /&gt;~ /zipcpu/trunk/bench/asm/lodsto.S&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Fri, 13 May 2016 02:00:56 +0100</pubDate>
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            <title>Updated the Makefile documentation and the all target.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=149</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 149 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Updated the Makefile documentation and the all target.&lt;/div&gt;~ /zipcpu/trunk/bench/cpp/Makefile&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Fri, 13 May 2016 01:56:01 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=149</guid>
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            <title>Minor changes to get LONG_MPY working, and adjust the documentation.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=148</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 148 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Minor changes to get LONG_MPY working, and adjust the documentation.&lt;/div&gt;~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Fri, 13 May 2016 01:55:23 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=148</guid>
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            <title>Cleans up div_tb a bit, causing it to write SUCCESS ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=147</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 147 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Cleans up div_tb a bit, causing it to write SUCCESS ...&lt;/div&gt;~ /zipcpu/trunk/bench/cpp/div_tb.cpp&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Fri, 13 May 2016 01:54:06 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=147</guid>
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            <title>Minor changes, but fixes build of zippy_tb.cpp.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=140</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 140 - dgisselq&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Minor changes, but fixes build of zippy_tb.cpp.&lt;/div&gt;~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp&lt;br /&gt;~ /zipcpu/trunk/rtl/core/idecode.v&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Mon, 09 May 2016 12:19:09 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=140</guid>
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        <item>
            <title>Working updates, to keep this up to date with the ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=134</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 134 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Working updates, to keep this up to date with the ...&lt;/div&gt;~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Fri, 22 Apr 2016 00:21:03 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=134</guid>
        </item>
        <item>
            <title>Fixed some nasty early branching bugs.  Adjusted the Makefile ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=105</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 105 - dgisselq&lt;/strong&gt; (7 file(s) modified)&lt;/div&gt;&lt;div&gt;Fixed some nasty early branching bugs.  Adjusted the Makefile ...&lt;/div&gt;~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp&lt;br /&gt;~ /zipcpu/trunk/rtl/core/idecode.v&lt;br /&gt;~ /zipcpu/trunk/rtl/core/idecode_deprecated.v&lt;br /&gt;~ /zipcpu/trunk/rtl/core/zipcpu.v&lt;br /&gt;~ /zipcpu/trunk/rtl/Makefile&lt;br /&gt;~ /zipcpu/trunk/rtl/zipbones.v&lt;br /&gt;~ /zipcpu/trunk/sw/zasm/test.S&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Wed, 09 Mar 2016 15:26:16 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=105</guid>
        </item>
        <item>
            <title>Adjusted the operator input line to reflect actual logic inputs, ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=87</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 87 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Adjusted the operator input line to reflect actual logic inputs, ...&lt;/div&gt;~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Sat, 02 Jan 2016 23:56:30 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=87</guid>
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            <description>&lt;div&gt;&lt;strong&gt;Rev 86 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Removed the requirement to have the dev.scope.cpu hardware defined outside&lt;br /&gt;
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            <author>dgisselq</author>
            <pubDate>Sat, 02 Jan 2016 23:55:01 +0100</pubDate>
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            <title>First check-in: the test bench for the divide instruction.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=77</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 77 - dgisselq&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;First check-in: the test bench for the divide instruction.&lt;/div&gt;+ /zipcpu/trunk/bench/cpp/div_tb.cpp&lt;br /&gt;</description>
            <author>dgisselq</author>
            <pubDate>Mon, 28 Dec 2015 20:53:32 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=zipcpu&amp;path=%2Fzipcpu%2Ftrunk%2Fbench%2F&amp;rev=77</guid>
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