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zipcpu WebSVN RSS feed - zipcpu https://opencores.org/websvn//websvn/listing?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F& Wed, 25 May 2022 15:17:16 +0100 FeedCreator 1.7.2 8b bytes, + formal verification throughout + dcache https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=209 <div><strong>Rev 209 - dgisselq</strong> (129 file(s) modified)</div><div>8b bytes, + formal verification throughout + dcache</div>+ /zipcpu/trunk/.gitignore<br />~ /zipcpu/trunk/bench/asm/Makefile<br />~ /zipcpu/trunk/bench/asm/zipdhry.S<br />~ /zipcpu/trunk/bench/cpp/helloworld.c<br />~ /zipcpu/trunk/bench/cpp/Makefile<br />+ /zipcpu/trunk/bench/cpp/README.md<br />+ /zipcpu/trunk/bench/formal<br />+ /zipcpu/trunk/bench/formal/.gitignore<br />+ /zipcpu/trunk/bench/formal/abs_div.v<br />+ /zipcpu/trunk/bench/formal/abs_mpy.v<br />+ /zipcpu/trunk/bench/formal/abs_prefetch.v<br />+ /zipcpu/trunk/bench/formal/busdelay.sby<br />+ /zipcpu/trunk/bench/formal/cpuops.sby<br />+ /zipcpu/trunk/bench/formal/dblfetch.sby<br />+ /zipcpu/trunk/bench/formal/dcache.gtkw<br />+ /zipcpu/trunk/bench/formal/dcache.sby<br />+ /zipcpu/trunk/bench/formal/div.gtkw<br />+ /zipcpu/trunk/bench/formal/div.sby<br />+ /zipcpu/trunk/bench/formal/f_idecode.v<br />+ /zipcpu/trunk/bench/formal/icontrol.sby<br />+ /zipcpu/trunk/bench/formal/idecode.gtkw<br />+ /zipcpu/trunk/bench/formal/idecode.sby<br />+ /zipcpu/trunk/bench/formal/Makefile<br />+ /zipcpu/trunk/bench/formal/mcve.sby<br />+ /zipcpu/trunk/bench/formal/mcve.v<br />+ /zipcpu/trunk/bench/formal/memops.sby<br />+ /zipcpu/trunk/bench/formal/pfcache.gtkw<br />+ /zipcpu/trunk/bench/formal/pfcache.sby<br />+ /zipcpu/trunk/bench/formal/pipemem.sby<br />+ /zipcpu/trunk/bench/formal/prefetch.sby<br />+ /zipcpu/trunk/bench/formal/wbdblpriarb.sby<br />+ /zipcpu/trunk/bench/formal/wbdmac.sby<br />+ /zipcpu/trunk/bench/formal/wbpriarbiter.sby<br />+ /zipcpu/trunk/bench/formal/wbwatchdog.sby<br />+ /zipcpu/trunk/bench/formal/zipcounter.sby<br />+ /zipcpu/trunk/bench/formal/zipcpu.gtkw<br />+ /zipcpu/trunk/bench/formal/zipcpu.sby<br />+ /zipcpu/trunk/bench/formal/zipjiffies.sby<br />+ /zipcpu/trunk/bench/formal/zipmmu.gtkw<br />+ /zipcpu/trunk/bench/formal/zipmmu.sby<br />+ /zipcpu/trunk/bench/formal/ziptimer.sby<br />+ /zipcpu/trunk/bench/rtl<br />+ /zipcpu/trunk/bench/rtl/Makefile<br />+ /zipcpu/trunk/bench/rtl/memdev.v<br />+ /zipcpu/trunk/bench/rtl/zipmmu_tb.v<br />+ /zipcpu/trunk/doc/.gitignore<br />+ /zipcpu/trunk/doc/gfx/.gitignore<br />~ /zipcpu/trunk/doc/gfx/cpu.dia<br />~ /zipcpu/trunk/doc/nextgen.html<br />~ /zipcpu/trunk/doc/orconf.pdf<br />+ /zipcpu/trunk/doc/orconf2017.pdf<br />+ /zipcpu/trunk/doc/orconf2018.pdf<br />~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br />~ /zipcpu/trunk/INSTALL.md<br />~ /zipcpu/trunk/Makefile<br />~ /zipcpu/trunk/README.md<br />~ /zipcpu/trunk/rtl/core<br />~ /zipcpu/trunk/rtl/core/cpuops.v<br />~ /zipcpu/trunk/rtl/core/dblfetch.v<br />~ /zipcpu/trunk/rtl/core/dcache.v<br />~ /zipcpu/trunk/rtl/core/div.v<br />~ /zipcpu/trunk/rtl/core/idecode.v<br />+ /zipcpu/trunk/rtl/core/iscachable.v<br />~ /zipcpu/trunk/rtl/core/memops.v<br />+ /zipcpu/trunk/rtl/core/mpyop.v<br />~ /zipcpu/trunk/rtl/core/pfcache.v<br />~ /zipcpu/trunk/rtl/core/pipefetch.v<br />~ /zipcpu/trunk/rtl/core/pipemem.v<br />~ /zipcpu/trunk/rtl/core/prefetch.v<br />+ /zipcpu/trunk/rtl/core/README.md<br />+ /zipcpu/trunk/rtl/core/slowmpy.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/cpudefs.v<br />+ /zipcpu/trunk/rtl/ex<br />+ /zipcpu/trunk/rtl/ex/busdelay.v<br />+ /zipcpu/trunk/rtl/ex/fwb_counter.v<br />+ /zipcpu/trunk/rtl/ex/fwb_master.v<br />+ /zipcpu/trunk/rtl/ex/fwb_slave.v<br />+ /zipcpu/trunk/rtl/ex/wbarbiter.v<br />+ /zipcpu/trunk/rtl/ex/wbdblpriarb.v<br />+ /zipcpu/trunk/rtl/ex/wbpriarbiter.v<br />~ /zipcpu/trunk/rtl/Makefile<br />~ /zipcpu/trunk/rtl/peripherals/icontrol.v<br />+ /zipcpu/trunk/rtl/peripherals/README.md<br />~ /zipcpu/trunk/rtl/peripherals/wbdmac.v<br />~ /zipcpu/trunk/rtl/peripherals/wbwatchdog.v<br />~ /zipcpu/trunk/rtl/peripherals/zipcounter.v<br />~ /zipcpu/trunk/rtl/peripherals/zipjiffies.v<br />~ /zipcpu/trunk/rtl/peripherals/zipmmu.v<br />~ /zipcpu/trunk/rtl/peripherals/ziptimer.v<br />+ /zipcpu/trunk/rtl/README.md<br />~ /zipcpu/trunk/rtl/zipbones.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br />~ /zipcpu/trunk/sim/cpp<br />~ /zipcpu/trunk/sim/cpp/Makefile<br />+ /zipcpu/trunk/sim/cpp/README.md<br />~ /zipcpu/trunk/sim/cpp/twoc.cpp<br />~ /zipcpu/trunk/sim/cpp/twoc.h<br />~ /zipcpu/trunk/sim/cpp/zipelf.cpp<br />~ /zipcpu/trunk/sim/cpp/zipelf.h<br />~ /zipcpu/trunk/sim/cpp/zsim.cpp<br />~ /zipcpu/trunk/sim/verilator<br />~ /zipcpu/trunk/sim/verilator/.gitignore<br />~ /zipcpu/trunk/sim/verilator/div_tb.cpp<br />~ /zipcpu/trunk/sim/verilator/Makefile<br />~ /zipcpu/trunk/sim/verilator/memsim.h<br />~ /zipcpu/trunk/sim/verilator/mpy_tb.cpp<br />~ /zipcpu/trunk/sim/verilator/pdump.cpp<br />~ /zipcpu/trunk/sim/verilator/pfcache_tb.cpp<br />+ /zipcpu/trunk/sim/verilator/README.md<br />~ /zipcpu/trunk/sim/verilator/testb.h<br />~ /zipcpu/trunk/sim/verilator/twoc.cpp<br />~ /zipcpu/trunk/sim/verilator/twoc.h<br />+ /zipcpu/trunk/sim/verilator/vversion.sh<br />+ /zipcpu/trunk/sim/verilator/zipcpu_tb.cpp<br />~ /zipcpu/trunk/sim/verilator/zipmmu_tb.cpp<br />~ /zipcpu/trunk/sw<br />~ /zipcpu/trunk/sw/.gitignore<br />~ /zipcpu/trunk/sw/gas-script.sh<br />~ /zipcpu/trunk/sw/gas-zippatch.patch<br />~ /zipcpu/trunk/sw/gcc-script.sh<br />~ /zipcpu/trunk/sw/gcc-zippatch.patch<br />~ /zipcpu/trunk/sw/Makefile<br />~ /zipcpu/trunk/sw/nlib-script.sh<br />~ /zipcpu/trunk/sw/nlib-zippatch.patch<br />+ /zipcpu/trunk/sw/README.md<br />~ /zipcpu/trunk/sw/zasm<br />~ /zipcpu/trunk/sw/zasm/.gitignore<br /> dgisselq Tue, 19 Mar 2019 03:24:12 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=209 Additional ZipCPU changes associated w 8b upgrade https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=202 <div><strong>Rev 202 - dgisselq</strong> (38 file(s) modified)</div><div>Additional ZipCPU changes associated w 8b upgrade</div>~ /zipcpu/trunk/bench/asm/cputest.c<br />~ /zipcpu/trunk/bench/asm/Makefile<br />~ /zipcpu/trunk/bench/asm/zipdhry.S<br />~ /zipcpu/trunk/bench/cpp/Makefile<br />~ /zipcpu/trunk/doc/gfx<br />+ /zipcpu/trunk/doc/gfx/bus-structure.eps<br />+ /zipcpu/trunk/doc/gfx/bus-structure.png<br />~ /zipcpu/trunk/doc/gfx/cpu.eps<br />+ /zipcpu/trunk/doc/gfx/zipbones.eps<br />- /zipcpu/trunk/doc/iset.html<br />~ /zipcpu/trunk/doc/Makefile<br />+ /zipcpu/trunk/doc/memsurvey.png<br />+ /zipcpu/trunk/doc/nextgen.html<br />+ /zipcpu/trunk/doc/nextgen.png<br />~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br />~ /zipcpu/trunk/Makefile<br />~ /zipcpu/trunk/sw<br />+ /zipcpu/trunk/sw/.gitignore<br />- /zipcpu/trunk/sw/binutils-2.25.patch<br />- /zipcpu/trunk/sw/binutils-2.25.tar.bz2<br />+ /zipcpu/trunk/sw/binutils-2.27.tar.bz2<br />~ /zipcpu/trunk/sw/gas-script.sh<br />+ /zipcpu/trunk/sw/gas-zippatch.patch<br />+ /zipcpu/trunk/sw/gcc-6.2.0.tar.bz2<br />~ /zipcpu/trunk/sw/gcc-script.sh<br />~ /zipcpu/trunk/sw/gcc-zippatch.patch<br />~ /zipcpu/trunk/sw/Makefile<br />+ /zipcpu/trunk/sw/newlib-2.5.0.tar.gz<br />+ /zipcpu/trunk/sw/nlib-script.sh<br />+ /zipcpu/trunk/sw/nlib-zippatch.patch<br />~ /zipcpu/trunk/sw/zasm<br />+ /zipcpu/trunk/sw/zasm/.gitignore<br />- /zipcpu/trunk/sw/zasm/obj-pc<br />+ /zipcpu/trunk/sw/zasm/README.md<br />~ /zipcpu/trunk/sw/zasm/zopcodes.cpp<br />~ /zipcpu/trunk/sw/zasm/zopcodes.h<br />~ /zipcpu/trunk/zip.vim<br /> dgisselq Thu, 09 Mar 2017 19:13:56 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=202 Massive specification rewrite, brings it up to date with the ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=199 <div><strong>Rev 199 - dgisselq</strong> (2 file(s) modified)</div><div>Massive specification rewrite, brings it up to date with the ...</div>~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br /> dgisselq Fri, 04 Nov 2016 22:53:44 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=199 Added the copyright statement back in. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=190 <div><strong>Rev 190 - dgisselq</strong> (1 file(s) modified)</div><div>Added the copyright statement back in.</div>~ /zipcpu/trunk/doc/Makefile<br /> dgisselq Mon, 17 Oct 2016 23:21:09 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=190 Final, as delivered, ORCONF slides. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=189 <div><strong>Rev 189 - dgisselq</strong> (1 file(s) modified)</div><div>Final, as delivered, ORCONF slides.</div>~ /zipcpu/trunk/doc/orconf.pdf<br /> dgisselq Mon, 17 Oct 2016 23:19:44 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=189 Adjusted the pdfinfo field, to accommodate Google's bot. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=173 <div><strong>Rev 173 - dgisselq</strong> (1 file(s) modified)</div><div>Adjusted the pdfinfo field, to accommodate Google's bot.</div>~ /zipcpu/trunk/doc/orconf.pdf<br /> dgisselq Thu, 15 Sep 2016 20:03:34 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=173 Minor updates to the orconf.pdf pre-conference slide. (Added the ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=170 <div><strong>Rev 170 - dgisselq</strong> (1 file(s) modified)</div><div>Minor updates to the orconf.pdf pre-conference slide. (Added the ...</div>~ /zipcpu/trunk/doc/orconf.pdf<br /> dgisselq Sat, 03 Sep 2016 20:32:47 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=170 Added details of LM32 to the (pre) ORConf survey slide ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=169 <div><strong>Rev 169 - dgisselq</strong> (1 file(s) modified)</div><div>Added details of LM32 to the (pre) ORConf survey slide ...</div>~ /zipcpu/trunk/doc/orconf.pdf<br /> dgisselq Fri, 29 Jul 2016 20:19:08 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=169 Updated the spec to reflect changes in the CC register: ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=167 <div><strong>Rev 167 - dgisselq</strong> (2 file(s) modified)</div><div>Updated the spec to reflect changes in the CC register: ...</div>~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br /> dgisselq Sat, 16 Jul 2016 20:25:05 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=167 Updated with inputs from Hellwig Geisse regarding the details of ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=164 <div><strong>Rev 164 - dgisselq</strong> (1 file(s) modified)</div><div>Updated with inputs from Hellwig Geisse regarding the details of ...</div>~ /zipcpu/trunk/doc/orconf.pdf<br /> dgisselq Fri, 08 Jul 2016 14:38:35 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=164 Trimmed OR1K instruction set down from 219 instructions, to the ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=163 <div><strong>Rev 163 - dgisselq</strong> (1 file(s) modified)</div><div>Trimmed OR1K instruction set down from 219 instructions, to the ...</div>~ /zipcpu/trunk/doc/orconf.pdf<br /> dgisselq Thu, 30 Jun 2016 12:39:16 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=163 Noted 64-bit integers are by extension, as are vector instructions. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=162 <div><strong>Rev 162 - dgisselq</strong> (1 file(s) modified)</div><div>Noted 64-bit integers are by extension, as are vector instructions.</div>~ /zipcpu/trunk/doc/orconf.pdf<br /> dgisselq Thu, 30 Jun 2016 11:58:27 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=162 Initial version of the ORConf slides, showing only the initial ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=161 <div><strong>Rev 161 - dgisselq</strong> (1 file(s) modified)</div><div>Initial version of the ORConf slides, showing only the initial ...</div>+ /zipcpu/trunk/doc/orconf.pdf<br /> dgisselq Thu, 30 Jun 2016 11:50:03 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=161 Adds internal link functionality to the specification document format. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=153 <div><strong>Rev 153 - dgisselq</strong> (1 file(s) modified)</div><div>Adds internal link functionality to the specification document format.</div>~ /zipcpu/trunk/doc/src/gqtekspec.cls<br /> dgisselq Wed, 15 Jun 2016 00:15:44 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=153 Changes necessary to document the changed instruction set: LDIHI became ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=139 <div><strong>Rev 139 - dgisselq</strong> (2 file(s) modified)</div><div>Changes necessary to document the changed instruction set: LDIHI became ...</div>~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br /> dgisselq Fri, 06 May 2016 15:01:59 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=139 Adding a missing file. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=107 <div><strong>Rev 107 - dgisselq</strong> (1 file(s) modified)</div><div>Adding a missing file.</div>+ /zipcpu/trunk/doc/gfx/mstld.eps<br /> dgisselq Mon, 14 Mar 2016 22:41:05 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=107 Updated to allow building without the sources for the graphics ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=106 <div><strong>Rev 106 - dgisselq</strong> (1 file(s) modified)</div><div>Updated to allow building without the sources for the graphics ...</div>~ /zipcpu/trunk/doc/Makefile<br /> dgisselq Mon, 14 Mar 2016 19:03:59 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=106 Adjustments made to match the simplified early branching. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=92 <div><strong>Rev 92 - dgisselq</strong> (2 file(s) modified)</div><div>Adjustments made to match the simplified early branching.</div>~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br /> dgisselq Thu, 28 Jan 2016 22:10:42 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=92 Minor update/correction to operand B definition. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=85 <div><strong>Rev 85 - dgisselq</strong> (1 file(s) modified)</div><div>Minor update/correction to operand B definition.</div>~ /zipcpu/trunk/doc/iset.html<br /> dgisselq Sat, 02 Jan 2016 23:53:54 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=85 Adjusted the opcodes for NOOP, BREAK, and LOCK. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=79 <div><strong>Rev 79 - dgisselq</strong> (1 file(s) modified)</div><div>Adjusted the opcodes for NOOP, BREAK, and LOCK.</div>~ /zipcpu/trunk/doc/iset.html<br /> dgisselq Tue, 29 Dec 2015 19:54:28 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=79
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