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zipcpu WebSVN RSS feed - zipcpu https://opencores.org/websvn//websvn/listing?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F& Wed, 29 Jun 2022 16:23:49 +0100 FeedCreator 1.7.2 Adjusted the pdfinfo field, to accommodate Google's bot. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=173 <div><strong>Rev 173 - dgisselq</strong> (1 file(s) modified)</div><div>Adjusted the pdfinfo field, to accommodate Google's bot.</div>~ /zipcpu/trunk/doc/orconf.pdf<br /> dgisselq Thu, 15 Sep 2016 20:03:34 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=173 Minor updates to the orconf.pdf pre-conference slide. (Added the ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=170 <div><strong>Rev 170 - dgisselq</strong> (1 file(s) modified)</div><div>Minor updates to the orconf.pdf pre-conference slide. (Added the ...</div>~ /zipcpu/trunk/doc/orconf.pdf<br /> dgisselq Sat, 03 Sep 2016 20:32:47 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=170 Added details of LM32 to the (pre) ORConf survey slide ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=169 <div><strong>Rev 169 - dgisselq</strong> (1 file(s) modified)</div><div>Added details of LM32 to the (pre) ORConf survey slide ...</div>~ /zipcpu/trunk/doc/orconf.pdf<br /> dgisselq Fri, 29 Jul 2016 20:19:08 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=169 Updated the spec to reflect changes in the CC register: ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=167 <div><strong>Rev 167 - dgisselq</strong> (2 file(s) modified)</div><div>Updated the spec to reflect changes in the CC register: ...</div>~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br /> dgisselq Sat, 16 Jul 2016 20:25:05 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=167 Updated with inputs from Hellwig Geisse regarding the details of ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=164 <div><strong>Rev 164 - dgisselq</strong> (1 file(s) modified)</div><div>Updated with inputs from Hellwig Geisse regarding the details of ...</div>~ /zipcpu/trunk/doc/orconf.pdf<br /> dgisselq Fri, 08 Jul 2016 14:38:35 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=164 Trimmed OR1K instruction set down from 219 instructions, to the ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=163 <div><strong>Rev 163 - dgisselq</strong> (1 file(s) modified)</div><div>Trimmed OR1K instruction set down from 219 instructions, to the ...</div>~ /zipcpu/trunk/doc/orconf.pdf<br /> dgisselq Thu, 30 Jun 2016 12:39:16 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=163 Noted 64-bit integers are by extension, as are vector instructions. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=162 <div><strong>Rev 162 - dgisselq</strong> (1 file(s) modified)</div><div>Noted 64-bit integers are by extension, as are vector instructions.</div>~ /zipcpu/trunk/doc/orconf.pdf<br /> dgisselq Thu, 30 Jun 2016 11:58:27 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=162 Initial version of the ORConf slides, showing only the initial ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=161 <div><strong>Rev 161 - dgisselq</strong> (1 file(s) modified)</div><div>Initial version of the ORConf slides, showing only the initial ...</div>+ /zipcpu/trunk/doc/orconf.pdf<br /> dgisselq Thu, 30 Jun 2016 11:50:03 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=161 Adds internal link functionality to the specification document format. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=153 <div><strong>Rev 153 - dgisselq</strong> (1 file(s) modified)</div><div>Adds internal link functionality to the specification document format.</div>~ /zipcpu/trunk/doc/src/gqtekspec.cls<br /> dgisselq Wed, 15 Jun 2016 00:15:44 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=153 Changes necessary to document the changed instruction set: LDIHI became ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=139 <div><strong>Rev 139 - dgisselq</strong> (2 file(s) modified)</div><div>Changes necessary to document the changed instruction set: LDIHI became ...</div>~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br /> dgisselq Fri, 06 May 2016 15:01:59 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=139 Adding a missing file. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=107 <div><strong>Rev 107 - dgisselq</strong> (1 file(s) modified)</div><div>Adding a missing file.</div>+ /zipcpu/trunk/doc/gfx/mstld.eps<br /> dgisselq Mon, 14 Mar 2016 22:41:05 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=107 Updated to allow building without the sources for the graphics ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=106 <div><strong>Rev 106 - dgisselq</strong> (1 file(s) modified)</div><div>Updated to allow building without the sources for the graphics ...</div>~ /zipcpu/trunk/doc/Makefile<br /> dgisselq Mon, 14 Mar 2016 19:03:59 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=106 Adjustments made to match the simplified early branching. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=92 <div><strong>Rev 92 - dgisselq</strong> (2 file(s) modified)</div><div>Adjustments made to match the simplified early branching.</div>~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br /> dgisselq Thu, 28 Jan 2016 22:10:42 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=92 Minor update/correction to operand B definition. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=85 <div><strong>Rev 85 - dgisselq</strong> (1 file(s) modified)</div><div>Minor update/correction to operand B definition.</div>~ /zipcpu/trunk/doc/iset.html<br /> dgisselq Sat, 02 Jan 2016 23:53:54 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=85 Adjusted the opcodes for NOOP, BREAK, and LOCK. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=79 <div><strong>Rev 79 - dgisselq</strong> (1 file(s) modified)</div><div>Adjusted the opcodes for NOOP, BREAK, and LOCK.</div>~ /zipcpu/trunk/doc/iset.html<br /> dgisselq Tue, 29 Dec 2015 19:54:28 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=79 Found/corrected annoying bug in floating point documentation of the opcode table. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=78 <div><strong>Rev 78 - dgisselq</strong> (1 file(s) modified)</div><div>Found/corrected annoying bug in floating point documentation of the opcode<br /> table.</div>~ /zipcpu/trunk/doc/iset.html<br /> dgisselq Tue, 29 Dec 2015 19:53:25 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=78 Documentations updates. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=73 <div><strong>Rev 73 - dgisselq</strong> (3 file(s) modified)</div><div>Documentations updates.</div>~ /zipcpu/trunk/doc/iset.html<br />~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br /> dgisselq Mon, 28 Dec 2015 20:39:21 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=73 Some updated graphics, now containing images of the CPU that ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=72 <div><strong>Rev 72 - dgisselq</strong> (4 file(s) modified)</div><div>Some updated graphics, now containing images of the CPU that ...</div>~ /zipcpu/trunk/doc/gfx/cpu.png<br />~ /zipcpu/trunk/doc/gfx/regset.png<br />~ /zipcpu/trunk/doc/gfx/system.png<br />~ /zipcpu/trunk/doc/gfx/zipbones.png<br /> dgisselq Mon, 28 Dec 2015 20:38:13 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=72 This implements the &quot;new Instruction Set&quot; architecture for the Zip ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=69 <div><strong>Rev 69 - dgisselq</strong> (85 file(s) modified)</div><div>This implements the &quot;new Instruction Set&quot; architecture for the Zip ...</div>~ /zipcpu/trunk/bench/asm/helloworld.S<br />~ /zipcpu/trunk/bench/asm/ivec.S<br />~ /zipcpu/trunk/bench/asm/lodsto.S<br />~ /zipcpu/trunk/bench/asm/Makefile<br />~ /zipcpu/trunk/bench/asm/pcpc.S<br />~ /zipcpu/trunk/bench/asm/testdiv.S<br />~ /zipcpu/trunk/bench/asm/wdt.S<br />~ /zipcpu/trunk/bench/asm/zipdhry.S<br />~ /zipcpu/trunk/bench/cpp/Makefile<br />~ /zipcpu/trunk/bench/cpp/memsim.cpp<br />~ /zipcpu/trunk/bench/cpp/memsim.h<br />~ /zipcpu/trunk/bench/cpp/pdump.cpp<br />~ /zipcpu/trunk/bench/cpp/testb.h<br />~ /zipcpu/trunk/bench/cpp/twoc.cpp<br />~ /zipcpu/trunk/bench/cpp/twoc.h<br />~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br />~ /zipcpu/trunk/doc/gfx/bc.eps<br />~ /zipcpu/trunk/doc/gfx/bra.eps<br />~ /zipcpu/trunk/doc/gfx/cpu.dia<br />~ /zipcpu/trunk/doc/gfx/cpu.eps<br />~ /zipcpu/trunk/doc/gfx/cpu.png<br />~ /zipcpu/trunk/doc/gfx/memrd.eps<br />~ /zipcpu/trunk/doc/gfx/memwr.eps<br />~ /zipcpu/trunk/doc/gfx/regset.png<br />~ /zipcpu/trunk/doc/gfx/system.dia<br />~ /zipcpu/trunk/doc/gfx/system.eps<br />~ /zipcpu/trunk/doc/gfx/system.png<br />~ /zipcpu/trunk/doc/gfx/zipbones.dia<br />~ /zipcpu/trunk/doc/gfx/zipbones.png<br />~ /zipcpu/trunk/doc/iset.html<br />~ /zipcpu/trunk/doc/Makefile<br />~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br />~ /zipcpu/trunk/Makefile<br />~ /zipcpu/trunk/rtl/aux/busdelay.v<br />~ /zipcpu/trunk/rtl/aux/wbarbiter.v<br />~ /zipcpu/trunk/rtl/aux/wbdblpriarb.v<br />~ /zipcpu/trunk/rtl/aux/wbpriarbiter.v<br />~ /zipcpu/trunk/rtl/core/cpuops.v<br />+ /zipcpu/trunk/rtl/core/cpuops_deprecated.v<br />+ /zipcpu/trunk/rtl/core/div.v<br />+ /zipcpu/trunk/rtl/core/idecode.v<br />+ /zipcpu/trunk/rtl/core/idecode_deprecated.v<br />~ /zipcpu/trunk/rtl/core/memops.v<br />+ /zipcpu/trunk/rtl/core/pfcache.v<br />~ /zipcpu/trunk/rtl/core/pipefetch.v<br />~ /zipcpu/trunk/rtl/core/pipemem.v<br />~ /zipcpu/trunk/rtl/core/prefetch.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/cpudefs.v<br />~ /zipcpu/trunk/rtl/Makefile<br />~ /zipcpu/trunk/rtl/peripherals/flashcache.v<br />~ /zipcpu/trunk/rtl/peripherals/icontrol.v<br />~ /zipcpu/trunk/rtl/peripherals/wbdmac.v<br />+ /zipcpu/trunk/rtl/peripherals/wbwatchdog.v<br />~ /zipcpu/trunk/rtl/peripherals/zipcounter.v<br />~ /zipcpu/trunk/rtl/peripherals/zipjiffies.v<br />~ /zipcpu/trunk/rtl/peripherals/ziptimer.v<br />~ /zipcpu/trunk/rtl/peripherals/ziptrap.v<br />~ /zipcpu/trunk/rtl/zipbones.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br />~ /zipcpu/trunk/sw/lib/divs.S<br />~ /zipcpu/trunk/sw/lib/divu.S<br />~ /zipcpu/trunk/sw/lib/mpy32s.S<br />~ /zipcpu/trunk/sw/lib/mpy32u.S<br />~ /zipcpu/trunk/sw/zasm/asmdata.cpp<br />~ /zipcpu/trunk/sw/zasm/asmdata.h<br />~ /zipcpu/trunk/sw/zasm/Makefile<br />~ /zipcpu/trunk/sw/zasm/optest.cpp<br />~ /zipcpu/trunk/sw/zasm/sys.i<br />~ /zipcpu/trunk/sw/zasm/test.S<br />~ /zipcpu/trunk/sw/zasm/twoc.cpp<br />~ /zipcpu/trunk/sw/zasm/twoc.h<br />~ /zipcpu/trunk/sw/zasm/zasm.l<br />~ /zipcpu/trunk/sw/zasm/zasm.y<br />~ /zipcpu/trunk/sw/zasm/zdump.cpp<br />~ /zipcpu/trunk/sw/zasm/zopcodes.cpp<br />~ /zipcpu/trunk/sw/zasm/zopcodes.h<br />~ /zipcpu/trunk/sw/zasm/zparser.cpp<br />~ /zipcpu/trunk/sw/zasm/zparser.h<br />~ /zipcpu/trunk/sw/zasm/zpp.l<br />~ /zipcpu/trunk/sw/zipdbg/devbus.h<br />~ /zipcpu/trunk/sw/zipdbg/regdefs.h<br />~ /zipcpu/trunk/sw/zipdbg/zipdbg.cpp<br />+ /zipcpu/trunk/zip.vim<br /> dgisselq Tue, 22 Dec 2015 16:06:51 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=69 Updated specification, includes well illustrated pipeline discussion. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=68 <div><strong>Rev 68 - dgisselq</strong> (3 file(s) modified)</div><div>Updated specification, includes well illustrated pipeline discussion.</div>~ /zipcpu/trunk/doc/Makefile<br />~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br /> dgisselq Tue, 17 Nov 2015 15:44:50 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=68
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