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https://opencores.org/websvn//websvn/listing?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&
Thu, 28 Mar 2024 19:47:19 +0100FeedCreator 1.7.2Added the copyright statement back in.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=190
<div><strong>Rev 190 - dgisselq</strong> (1 file(s) modified)</div><div>Added the copyright statement back in.</div>~ /zipcpu/trunk/doc/Makefile<br />dgisselqMon, 17 Oct 2016 23:21:09 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=190Final, as delivered, ORCONF slides.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=189
<div><strong>Rev 189 - dgisselq</strong> (1 file(s) modified)</div><div>Final, as delivered, ORCONF slides.</div>~ /zipcpu/trunk/doc/orconf.pdf<br />dgisselqMon, 17 Oct 2016 23:19:44 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=189Adjusted the pdfinfo field, to accommodate Google's bot.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=173
<div><strong>Rev 173 - dgisselq</strong> (1 file(s) modified)</div><div>Adjusted the pdfinfo field, to accommodate Google's bot.</div>~ /zipcpu/trunk/doc/orconf.pdf<br />dgisselqThu, 15 Sep 2016 20:03:34 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=173Minor updates to the orconf.pdf pre-conference slide. (Added the ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=170
<div><strong>Rev 170 - dgisselq</strong> (1 file(s) modified)</div><div>Minor updates to the orconf.pdf pre-conference slide. (Added the ...</div>~ /zipcpu/trunk/doc/orconf.pdf<br />dgisselqSat, 03 Sep 2016 20:32:47 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=170Added details of LM32 to the (pre) ORConf survey slide ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=169
<div><strong>Rev 169 - dgisselq</strong> (1 file(s) modified)</div><div>Added details of LM32 to the (pre) ORConf survey slide ...</div>~ /zipcpu/trunk/doc/orconf.pdf<br />dgisselqFri, 29 Jul 2016 20:19:08 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=169Updated the spec to reflect changes in the CC register: ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=167
<div><strong>Rev 167 - dgisselq</strong> (2 file(s) modified)</div><div>Updated the spec to reflect changes in the CC register: ...</div>~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br />dgisselqSat, 16 Jul 2016 20:25:05 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=167Updated with inputs from Hellwig Geisse regarding the details of ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=164
<div><strong>Rev 164 - dgisselq</strong> (1 file(s) modified)</div><div>Updated with inputs from Hellwig Geisse regarding the details of ...</div>~ /zipcpu/trunk/doc/orconf.pdf<br />dgisselqFri, 08 Jul 2016 14:38:35 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=164Trimmed OR1K instruction set down from 219 instructions, to the ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=163
<div><strong>Rev 163 - dgisselq</strong> (1 file(s) modified)</div><div>Trimmed OR1K instruction set down from 219 instructions, to the ...</div>~ /zipcpu/trunk/doc/orconf.pdf<br />dgisselqThu, 30 Jun 2016 12:39:16 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=163Noted 64-bit integers are by extension, as are vector instructions.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=162
<div><strong>Rev 162 - dgisselq</strong> (1 file(s) modified)</div><div>Noted 64-bit integers are by extension, as are vector instructions.</div>~ /zipcpu/trunk/doc/orconf.pdf<br />dgisselqThu, 30 Jun 2016 11:58:27 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=162Initial version of the ORConf slides, showing only the initial ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=161
<div><strong>Rev 161 - dgisselq</strong> (1 file(s) modified)</div><div>Initial version of the ORConf slides, showing only the initial ...</div>+ /zipcpu/trunk/doc/orconf.pdf<br />dgisselqThu, 30 Jun 2016 11:50:03 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=161Adds internal link functionality to the specification document format.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=153
<div><strong>Rev 153 - dgisselq</strong> (1 file(s) modified)</div><div>Adds internal link functionality to the specification document format.</div>~ /zipcpu/trunk/doc/src/gqtekspec.cls<br />dgisselqWed, 15 Jun 2016 00:15:44 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=153Changes necessary to document the changed instruction set: LDIHI became ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=139
<div><strong>Rev 139 - dgisselq</strong> (2 file(s) modified)</div><div>Changes necessary to document the changed instruction set: LDIHI became ...</div>~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br />dgisselqFri, 06 May 2016 15:01:59 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=139Adding a missing file.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=107
<div><strong>Rev 107 - dgisselq</strong> (1 file(s) modified)</div><div>Adding a missing file.</div>+ /zipcpu/trunk/doc/gfx/mstld.eps<br />dgisselqMon, 14 Mar 2016 22:41:05 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=107Updated to allow building without the sources for the graphics ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=106
<div><strong>Rev 106 - dgisselq</strong> (1 file(s) modified)</div><div>Updated to allow building without the sources for the graphics ...</div>~ /zipcpu/trunk/doc/Makefile<br />dgisselqMon, 14 Mar 2016 19:03:59 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=106Adjustments made to match the simplified early branching.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=92
<div><strong>Rev 92 - dgisselq</strong> (2 file(s) modified)</div><div>Adjustments made to match the simplified early branching.</div>~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br />dgisselqThu, 28 Jan 2016 22:10:42 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=92Minor update/correction to operand B definition.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=85
<div><strong>Rev 85 - dgisselq</strong> (1 file(s) modified)</div><div>Minor update/correction to operand B definition.</div>~ /zipcpu/trunk/doc/iset.html<br />dgisselqSat, 02 Jan 2016 23:53:54 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=85Adjusted the opcodes for NOOP, BREAK, and LOCK.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=79
<div><strong>Rev 79 - dgisselq</strong> (1 file(s) modified)</div><div>Adjusted the opcodes for NOOP, BREAK, and LOCK.</div>~ /zipcpu/trunk/doc/iset.html<br />dgisselqTue, 29 Dec 2015 19:54:28 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=79Found/corrected annoying bug in floating point documentation of the opcode
table.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=78
<div><strong>Rev 78 - dgisselq</strong> (1 file(s) modified)</div><div>Found/corrected annoying bug in floating point documentation of the opcode<br />
table.</div>~ /zipcpu/trunk/doc/iset.html<br />dgisselqTue, 29 Dec 2015 19:53:25 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=78Documentations updates.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=73
<div><strong>Rev 73 - dgisselq</strong> (3 file(s) modified)</div><div>Documentations updates.</div>~ /zipcpu/trunk/doc/iset.html<br />~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br />dgisselqMon, 28 Dec 2015 20:39:21 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=73Some updated graphics, now containing images of the CPU that ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=72
<div><strong>Rev 72 - dgisselq</strong> (4 file(s) modified)</div><div>Some updated graphics, now containing images of the CPU that ...</div>~ /zipcpu/trunk/doc/gfx/cpu.png<br />~ /zipcpu/trunk/doc/gfx/regset.png<br />~ /zipcpu/trunk/doc/gfx/system.png<br />~ /zipcpu/trunk/doc/gfx/zipbones.png<br />dgisselqMon, 28 Dec 2015 20:38:13 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fdoc%2F&rev=72