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https://opencores.org/websvn//websvn/listing?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&
Thu, 28 Mar 2024 20:10:52 +0100FeedCreator 1.7.2Bug fix for fast memories. This now works for ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=182
<div><strong>Rev 182 - dgisselq</strong> (1 file(s) modified)</div><div>Bug fix for fast memories. This now works for ...</div>~ /zipcpu/trunk/rtl/peripherals/wbdmac.v<br />dgisselqThu, 15 Sep 2016 20:23:00 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=182Adjusted the wishbone logic to include our wishbone simplification that ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=181
<div><strong>Rev 181 - dgisselq</strong> (1 file(s) modified)</div><div>Adjusted the wishbone logic to include our wishbone simplification that ...</div>~ /zipcpu/trunk/rtl/peripherals/zipcounter.v<br />dgisselqThu, 15 Sep 2016 20:21:22 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=181Cleaned up the stall logic--made it independent of whether or ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=180
<div><strong>Rev 180 - dgisselq</strong> (1 file(s) modified)</div><div>Cleaned up the stall logic--made it independent of whether or ...</div>~ /zipcpu/trunk/rtl/aux/wbarbiter.v<br />dgisselqThu, 15 Sep 2016 20:20:36 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=180Lots of changes, most (all?) of them to the non-pipelined ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=179
<div><strong>Rev 179 - dgisselq</strong> (1 file(s) modified)</div><div>Lots of changes, most (all?) of them to the non-pipelined ...</div>~ /zipcpu/trunk/rtl/core/zipcpu.v<br />dgisselqThu, 15 Sep 2016 20:18:45 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=179Rewrote the parameter controlled logic to be just that: perameter ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=178
<div><strong>Rev 178 - dgisselq</strong> (1 file(s) modified)</div><div>Rewrote the parameter controlled logic to be just that: perameter ...</div>~ /zipcpu/trunk/rtl/core/idecode.v<br />dgisselqThu, 15 Sep 2016 20:17:36 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=178Fixed the illegal address logic to be more precise.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=177
<div><strong>Rev 177 - dgisselq</strong> (1 file(s) modified)</div><div>Fixed the illegal address logic to be more precise.</div>~ /zipcpu/trunk/rtl/core/pipefetch.v<br />dgisselqThu, 15 Sep 2016 20:14:26 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=177Switched from distributed to block RAM, and adjusted the logic ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=176
<div><strong>Rev 176 - dgisselq</strong> (1 file(s) modified)</div><div>Switched from distributed to block RAM, and adjusted the logic ...</div>~ /zipcpu/trunk/rtl/core/pfcache.v<br />dgisselqThu, 15 Sep 2016 20:13:17 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=176Fixed the carry bit for logical shifts: it is the ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=175
<div><strong>Rev 175 - dgisselq</strong> (1 file(s) modified)</div><div>Fixed the carry bit for logical shifts: it is the ...</div>~ /zipcpu/trunk/rtl/core/cpuops.v<br />dgisselqThu, 15 Sep 2016 20:10:53 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=175Simplified the divide to improve timing performance.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=174
<div><strong>Rev 174 - dgisselq</strong> (1 file(s) modified)</div><div>Simplified the divide to improve timing performance.</div>~ /zipcpu/trunk/rtl/core/div.v<br />dgisselqThu, 15 Sep 2016 20:06:48 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=174Logic updates, and bug fix corrections to bring this in ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=160
<div><strong>Rev 160 - dgisselq</strong> (8 file(s) modified)</div><div>Logic updates, and bug fix corrections to bring this in ...</div>~ /zipcpu/trunk/rtl/core/div.v<br />~ /zipcpu/trunk/rtl/core/idecode.v<br />~ /zipcpu/trunk/rtl/core/pipemem.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/peripherals/wbdmac.v<br />~ /zipcpu/trunk/rtl/peripherals/zipcounter.v<br />~ /zipcpu/trunk/rtl/peripherals/zipjiffies.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br />dgisselqWed, 15 Jun 2016 00:28:39 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=160Added the divide unit to the list of ZipCPU dependencies.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=157
<div><strong>Rev 157 - dgisselq</strong> (1 file(s) modified)</div><div>Added the divide unit to the list of ZipCPU dependencies.</div>~ /zipcpu/trunk/rtl/Makefile<br />dgisselqWed, 15 Jun 2016 00:22:25 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=157This fixes the pipelined memory problem that was introduced a ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=145
<div><strong>Rev 145 - dgisselq</strong> (1 file(s) modified)</div><div>This fixes the pipelined memory problem that was introduced a ...</div>~ /zipcpu/trunk/rtl/core/zipcpu.v<br />dgisselqFri, 13 May 2016 01:42:59 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=145Makes the auto-reload capability a configuration option, and fills out ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=144
<div><strong>Rev 144 - dgisselq</strong> (1 file(s) modified)</div><div>Makes the auto-reload capability a configuration option, and fills out ...</div>~ /zipcpu/trunk/rtl/peripherals/ziptimer.v<br />dgisselqFri, 13 May 2016 01:32:46 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=144Minor changes, but fixes build of zippy_tb.cpp.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=140
<div><strong>Rev 140 - dgisselq</strong> (2 file(s) modified)</div><div>Minor changes, but fixes build of zippy_tb.cpp.</div>~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br />~ /zipcpu/trunk/rtl/core/idecode.v<br />dgisselqMon, 09 May 2016 12:19:09 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=140This updates the CPU multiply instruction into a set of ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=138
<div><strong>Rev 138 - dgisselq</strong> (5 file(s) modified)</div><div>This updates the CPU multiply instruction into a set of ...</div>~ /zipcpu/trunk/rtl/core/cpuops.v<br />~ /zipcpu/trunk/rtl/core/idecode.v<br />~ /zipcpu/trunk/rtl/cpudefs.v<br />~ /zipcpu/trunk/sw/binutils-2.25.patch<br />~ /zipcpu/trunk/sw/gcc-zippatch.patch<br />dgisselqFri, 06 May 2016 14:54:30 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=138Changes preceding an instruction set update, which will change the ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=133
<div><strong>Rev 133 - dgisselq</strong> (1 file(s) modified)</div><div>Changes preceding an instruction set update, which will change the ...</div>~ /zipcpu/trunk/rtl/core/cpuops.v<br />dgisselqFri, 22 Apr 2016 00:19:39 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=133Lots of minor bug fixes.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=132
<div><strong>Rev 132 - dgisselq</strong> (1 file(s) modified)</div><div>Lots of minor bug fixes.</div>~ /zipcpu/trunk/rtl/core/zipcpu.v<br />dgisselqFri, 22 Apr 2016 00:17:59 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=132Fixed a variable use before declaration error.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=131
<div><strong>Rev 131 - dgisselq</strong> (1 file(s) modified)</div><div>Fixed a variable use before declaration error.</div>~ /zipcpu/trunk/rtl/core/pipemem.v<br />dgisselqFri, 22 Apr 2016 00:13:00 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=131Simplified the lock logic, and removed it when pipelining was ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=130
<div><strong>Rev 130 - dgisselq</strong> (1 file(s) modified)</div><div>Simplified the lock logic, and removed it when pipelining was ...</div>~ /zipcpu/trunk/rtl/core/idecode.v<br />dgisselqFri, 22 Apr 2016 00:12:28 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=130Bug fix. Fixes some ugly race conditions that would ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=129
<div><strong>Rev 129 - dgisselq</strong> (1 file(s) modified)</div><div>Bug fix. Fixes some ugly race conditions that would ...</div>~ /zipcpu/trunk/rtl/core/pfcache.v<br />dgisselqFri, 22 Apr 2016 00:10:27 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=129