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zipcpu WebSVN RSS feed - zipcpu https://opencores.org/websvn//websvn/listing?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F& Sat, 28 May 2022 04:29:44 +0100 FeedCreator 1.7.2 Adjusted the illegal instruction option documentation. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=184 <div><strong>Rev 184 - dgisselq</strong> (1 file(s) modified)</div><div>Adjusted the illegal instruction option documentation.</div>~ /zipcpu/trunk/rtl/cpudefs.v<br /> dgisselq Thu, 15 Sep 2016 20:24:56 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=184 Cleaned up the system so that !CYC implies !STB as ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=183 <div><strong>Rev 183 - dgisselq</strong> (2 file(s) modified)</div><div>Cleaned up the system so that !CYC implies !STB as ...</div>~ /zipcpu/trunk/rtl/zipbones.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br /> dgisselq Thu, 15 Sep 2016 20:24:05 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=183 Bug fix for fast memories. This now works for ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=182 <div><strong>Rev 182 - dgisselq</strong> (1 file(s) modified)</div><div>Bug fix for fast memories. This now works for ...</div>~ /zipcpu/trunk/rtl/peripherals/wbdmac.v<br /> dgisselq Thu, 15 Sep 2016 20:23:00 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=182 Adjusted the wishbone logic to include our wishbone simplification that ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=181 <div><strong>Rev 181 - dgisselq</strong> (1 file(s) modified)</div><div>Adjusted the wishbone logic to include our wishbone simplification that ...</div>~ /zipcpu/trunk/rtl/peripherals/zipcounter.v<br /> dgisselq Thu, 15 Sep 2016 20:21:22 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=181 Cleaned up the stall logic--made it independent of whether or ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=180 <div><strong>Rev 180 - dgisselq</strong> (1 file(s) modified)</div><div>Cleaned up the stall logic--made it independent of whether or ...</div>~ /zipcpu/trunk/rtl/aux/wbarbiter.v<br /> dgisselq Thu, 15 Sep 2016 20:20:36 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=180 Lots of changes, most (all?) of them to the non-pipelined ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=179 <div><strong>Rev 179 - dgisselq</strong> (1 file(s) modified)</div><div>Lots of changes, most (all?) of them to the non-pipelined ...</div>~ /zipcpu/trunk/rtl/core/zipcpu.v<br /> dgisselq Thu, 15 Sep 2016 20:18:45 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=179 Rewrote the parameter controlled logic to be just that: perameter ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=178 <div><strong>Rev 178 - dgisselq</strong> (1 file(s) modified)</div><div>Rewrote the parameter controlled logic to be just that: perameter ...</div>~ /zipcpu/trunk/rtl/core/idecode.v<br /> dgisselq Thu, 15 Sep 2016 20:17:36 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=178 Fixed the illegal address logic to be more precise. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=177 <div><strong>Rev 177 - dgisselq</strong> (1 file(s) modified)</div><div>Fixed the illegal address logic to be more precise.</div>~ /zipcpu/trunk/rtl/core/pipefetch.v<br /> dgisselq Thu, 15 Sep 2016 20:14:26 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=177 Switched from distributed to block RAM, and adjusted the logic ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=176 <div><strong>Rev 176 - dgisselq</strong> (1 file(s) modified)</div><div>Switched from distributed to block RAM, and adjusted the logic ...</div>~ /zipcpu/trunk/rtl/core/pfcache.v<br /> dgisselq Thu, 15 Sep 2016 20:13:17 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=176 Fixed the carry bit for logical shifts: it is the ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=175 <div><strong>Rev 175 - dgisselq</strong> (1 file(s) modified)</div><div>Fixed the carry bit for logical shifts: it is the ...</div>~ /zipcpu/trunk/rtl/core/cpuops.v<br /> dgisselq Thu, 15 Sep 2016 20:10:53 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=175 Simplified the divide to improve timing performance. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=174 <div><strong>Rev 174 - dgisselq</strong> (1 file(s) modified)</div><div>Simplified the divide to improve timing performance.</div>~ /zipcpu/trunk/rtl/core/div.v<br /> dgisselq Thu, 15 Sep 2016 20:06:48 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=174 Logic updates, and bug fix corrections to bring this in ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=160 <div><strong>Rev 160 - dgisselq</strong> (8 file(s) modified)</div><div>Logic updates, and bug fix corrections to bring this in ...</div>~ /zipcpu/trunk/rtl/core/div.v<br />~ /zipcpu/trunk/rtl/core/idecode.v<br />~ /zipcpu/trunk/rtl/core/pipemem.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/peripherals/wbdmac.v<br />~ /zipcpu/trunk/rtl/peripherals/zipcounter.v<br />~ /zipcpu/trunk/rtl/peripherals/zipjiffies.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br /> dgisselq Wed, 15 Jun 2016 00:28:39 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=160 Added the divide unit to the list of ZipCPU dependencies. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=157 <div><strong>Rev 157 - dgisselq</strong> (1 file(s) modified)</div><div>Added the divide unit to the list of ZipCPU dependencies.</div>~ /zipcpu/trunk/rtl/Makefile<br /> dgisselq Wed, 15 Jun 2016 00:22:25 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=157 This fixes the pipelined memory problem that was introduced a ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=145 <div><strong>Rev 145 - dgisselq</strong> (1 file(s) modified)</div><div>This fixes the pipelined memory problem that was introduced a ...</div>~ /zipcpu/trunk/rtl/core/zipcpu.v<br /> dgisselq Fri, 13 May 2016 01:42:59 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=145 Makes the auto-reload capability a configuration option, and fills out ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=144 <div><strong>Rev 144 - dgisselq</strong> (1 file(s) modified)</div><div>Makes the auto-reload capability a configuration option, and fills out ...</div>~ /zipcpu/trunk/rtl/peripherals/ziptimer.v<br /> dgisselq Fri, 13 May 2016 01:32:46 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=144 Minor changes, but fixes build of zippy_tb.cpp. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=140 <div><strong>Rev 140 - dgisselq</strong> (2 file(s) modified)</div><div>Minor changes, but fixes build of zippy_tb.cpp.</div>~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br />~ /zipcpu/trunk/rtl/core/idecode.v<br /> dgisselq Mon, 09 May 2016 12:19:09 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=140 This updates the CPU multiply instruction into a set of ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=138 <div><strong>Rev 138 - dgisselq</strong> (5 file(s) modified)</div><div>This updates the CPU multiply instruction into a set of ...</div>~ /zipcpu/trunk/rtl/core/cpuops.v<br />~ /zipcpu/trunk/rtl/core/idecode.v<br />~ /zipcpu/trunk/rtl/cpudefs.v<br />~ /zipcpu/trunk/sw/binutils-2.25.patch<br />~ /zipcpu/trunk/sw/gcc-zippatch.patch<br /> dgisselq Fri, 06 May 2016 14:54:30 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=138 Changes preceding an instruction set update, which will change the ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=133 <div><strong>Rev 133 - dgisselq</strong> (1 file(s) modified)</div><div>Changes preceding an instruction set update, which will change the ...</div>~ /zipcpu/trunk/rtl/core/cpuops.v<br /> dgisselq Fri, 22 Apr 2016 00:19:39 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=133 Lots of minor bug fixes. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=132 <div><strong>Rev 132 - dgisselq</strong> (1 file(s) modified)</div><div>Lots of minor bug fixes.</div>~ /zipcpu/trunk/rtl/core/zipcpu.v<br /> dgisselq Fri, 22 Apr 2016 00:17:59 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=132 Fixed a variable use before declaration error. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=131 <div><strong>Rev 131 - dgisselq</strong> (1 file(s) modified)</div><div>Fixed a variable use before declaration error.</div>~ /zipcpu/trunk/rtl/core/pipemem.v<br /> dgisselq Fri, 22 Apr 2016 00:13:00 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=131
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