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https://opencores.org/websvn//websvn/listing?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&
Fri, 29 Mar 2024 14:11:56 +0100FeedCreator 1.7.2Updating core to current/best version, to include dblfetch support and ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=205
<div><strong>Rev 205 - dgisselq</strong> (8 file(s) modified)</div><div>Updating core to current/best version, to include dblfetch support and ...</div>~ /zipcpu/trunk/rtl/core/cpuops.v<br />+ /zipcpu/trunk/rtl/core/dblfetch.v<br />~ /zipcpu/trunk/rtl/core/div.v<br />~ /zipcpu/trunk/rtl/core/idecode.v<br />~ /zipcpu/trunk/rtl/core/memops.v<br />~ /zipcpu/trunk/rtl/core/prefetch.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/cpudefs.v<br />dgisselqTue, 28 Mar 2017 15:26:49 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=205RTL files for the 8-bit capable ZipCPU.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=201
<div><strong>Rev 201 - dgisselq</strong> (30 file(s) modified)</div><div>RTL files for the 8-bit capable ZipCPU.</div>~ /zipcpu/trunk/rtl<br />~ /zipcpu/trunk/rtl/aux/busdelay.v<br />~ /zipcpu/trunk/rtl/aux/wbarbiter.v<br />~ /zipcpu/trunk/rtl/aux/wbdblpriarb.v<br />~ /zipcpu/trunk/rtl/aux/wbpriarbiter.v<br />~ /zipcpu/trunk/rtl/core/cpuops.v<br />- /zipcpu/trunk/rtl/core/cpuops_deprecated.v<br />+ /zipcpu/trunk/rtl/core/dcache.v<br />~ /zipcpu/trunk/rtl/core/div.v<br />~ /zipcpu/trunk/rtl/core/idecode.v<br />- /zipcpu/trunk/rtl/core/idecode_deprecated.v<br />~ /zipcpu/trunk/rtl/core/memops.v<br />~ /zipcpu/trunk/rtl/core/pfcache.v<br />~ /zipcpu/trunk/rtl/core/pipefetch.v<br />~ /zipcpu/trunk/rtl/core/pipemem.v<br />~ /zipcpu/trunk/rtl/core/prefetch.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/cpudefs.v<br />~ /zipcpu/trunk/rtl/Makefile<br />~ /zipcpu/trunk/rtl/peripherals<br />~ /zipcpu/trunk/rtl/peripherals/flashcache.v<br />~ /zipcpu/trunk/rtl/peripherals/icontrol.v<br />~ /zipcpu/trunk/rtl/peripherals/wbdmac.v<br />~ /zipcpu/trunk/rtl/peripherals/wbwatchdog.v<br />~ /zipcpu/trunk/rtl/peripherals/zipcounter.v<br />~ /zipcpu/trunk/rtl/peripherals/zipjiffies.v<br />+ /zipcpu/trunk/rtl/peripherals/zipmmu.v<br />~ /zipcpu/trunk/rtl/peripherals/ziptimer.v<br />~ /zipcpu/trunk/rtl/zipbones.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br />dgisselqThu, 09 Mar 2017 18:08:47 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=201Updated internal documentation.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=196
<div><strong>Rev 196 - dgisselq</strong> (1 file(s) modified)</div><div>Updated internal documentation.</div>~ /zipcpu/trunk/rtl/core/div.v<br />dgisselqThu, 03 Nov 2016 18:21:53 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=196Adds a new mode that can handle a delayed stall ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=195
<div><strong>Rev 195 - dgisselq</strong> (1 file(s) modified)</div><div>Adds a new mode that can handle a delayed stall ...</div>~ /zipcpu/trunk/rtl/aux/busdelay.v<br />dgisselqThu, 03 Nov 2016 18:21:30 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=195Cleaned up some parameters, trying to create more consistency.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=194
<div><strong>Rev 194 - dgisselq</strong> (3 file(s) modified)</div><div>Cleaned up some parameters, trying to create more consistency.</div>~ /zipcpu/trunk/rtl/core/pfcache.v<br />~ /zipcpu/trunk/rtl/core/pipemem.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br />dgisselqThu, 03 Nov 2016 18:20:42 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=194These changes make it so the ALU multiplies pass a ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=193
<div><strong>Rev 193 - dgisselq</strong> (4 file(s) modified)</div><div>These changes make it so the ALU multiplies pass a ...</div>~ /zipcpu/trunk/rtl/core/cpuops.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/cpudefs.v<br />~ /zipcpu/trunk/rtl/Makefile<br />dgisselqThu, 03 Nov 2016 18:19:37 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=193Adjusted the illegal instruction option documentation.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=184
<div><strong>Rev 184 - dgisselq</strong> (1 file(s) modified)</div><div>Adjusted the illegal instruction option documentation.</div>~ /zipcpu/trunk/rtl/cpudefs.v<br />dgisselqThu, 15 Sep 2016 20:24:56 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=184Cleaned up the system so that !CYC implies !STB as ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=183
<div><strong>Rev 183 - dgisselq</strong> (2 file(s) modified)</div><div>Cleaned up the system so that !CYC implies !STB as ...</div>~ /zipcpu/trunk/rtl/zipbones.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br />dgisselqThu, 15 Sep 2016 20:24:05 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=183Bug fix for fast memories. This now works for ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=182
<div><strong>Rev 182 - dgisselq</strong> (1 file(s) modified)</div><div>Bug fix for fast memories. This now works for ...</div>~ /zipcpu/trunk/rtl/peripherals/wbdmac.v<br />dgisselqThu, 15 Sep 2016 20:23:00 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=182Adjusted the wishbone logic to include our wishbone simplification that ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=181
<div><strong>Rev 181 - dgisselq</strong> (1 file(s) modified)</div><div>Adjusted the wishbone logic to include our wishbone simplification that ...</div>~ /zipcpu/trunk/rtl/peripherals/zipcounter.v<br />dgisselqThu, 15 Sep 2016 20:21:22 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=181Cleaned up the stall logic--made it independent of whether or ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=180
<div><strong>Rev 180 - dgisselq</strong> (1 file(s) modified)</div><div>Cleaned up the stall logic--made it independent of whether or ...</div>~ /zipcpu/trunk/rtl/aux/wbarbiter.v<br />dgisselqThu, 15 Sep 2016 20:20:36 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=180Lots of changes, most (all?) of them to the non-pipelined ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=179
<div><strong>Rev 179 - dgisselq</strong> (1 file(s) modified)</div><div>Lots of changes, most (all?) of them to the non-pipelined ...</div>~ /zipcpu/trunk/rtl/core/zipcpu.v<br />dgisselqThu, 15 Sep 2016 20:18:45 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=179Rewrote the parameter controlled logic to be just that: perameter ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=178
<div><strong>Rev 178 - dgisselq</strong> (1 file(s) modified)</div><div>Rewrote the parameter controlled logic to be just that: perameter ...</div>~ /zipcpu/trunk/rtl/core/idecode.v<br />dgisselqThu, 15 Sep 2016 20:17:36 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=178Fixed the illegal address logic to be more precise.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=177
<div><strong>Rev 177 - dgisselq</strong> (1 file(s) modified)</div><div>Fixed the illegal address logic to be more precise.</div>~ /zipcpu/trunk/rtl/core/pipefetch.v<br />dgisselqThu, 15 Sep 2016 20:14:26 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=177Switched from distributed to block RAM, and adjusted the logic ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=176
<div><strong>Rev 176 - dgisselq</strong> (1 file(s) modified)</div><div>Switched from distributed to block RAM, and adjusted the logic ...</div>~ /zipcpu/trunk/rtl/core/pfcache.v<br />dgisselqThu, 15 Sep 2016 20:13:17 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=176Fixed the carry bit for logical shifts: it is the ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=175
<div><strong>Rev 175 - dgisselq</strong> (1 file(s) modified)</div><div>Fixed the carry bit for logical shifts: it is the ...</div>~ /zipcpu/trunk/rtl/core/cpuops.v<br />dgisselqThu, 15 Sep 2016 20:10:53 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=175Simplified the divide to improve timing performance.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=174
<div><strong>Rev 174 - dgisselq</strong> (1 file(s) modified)</div><div>Simplified the divide to improve timing performance.</div>~ /zipcpu/trunk/rtl/core/div.v<br />dgisselqThu, 15 Sep 2016 20:06:48 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=174Logic updates, and bug fix corrections to bring this in ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=160
<div><strong>Rev 160 - dgisselq</strong> (8 file(s) modified)</div><div>Logic updates, and bug fix corrections to bring this in ...</div>~ /zipcpu/trunk/rtl/core/div.v<br />~ /zipcpu/trunk/rtl/core/idecode.v<br />~ /zipcpu/trunk/rtl/core/pipemem.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/peripherals/wbdmac.v<br />~ /zipcpu/trunk/rtl/peripherals/zipcounter.v<br />~ /zipcpu/trunk/rtl/peripherals/zipjiffies.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br />dgisselqWed, 15 Jun 2016 00:28:39 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=160Added the divide unit to the list of ZipCPU dependencies.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=157
<div><strong>Rev 157 - dgisselq</strong> (1 file(s) modified)</div><div>Added the divide unit to the list of ZipCPU dependencies.</div>~ /zipcpu/trunk/rtl/Makefile<br />dgisselqWed, 15 Jun 2016 00:22:25 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=157This fixes the pipelined memory problem that was introduced a ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=145
<div><strong>Rev 145 - dgisselq</strong> (1 file(s) modified)</div><div>This fixes the pipelined memory problem that was introduced a ...</div>~ /zipcpu/trunk/rtl/core/zipcpu.v<br />dgisselqFri, 13 May 2016 01:42:59 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2F&rev=145