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zipcpu WebSVN RSS feed - zipcpu https://opencores.org/websvn//websvn/listing?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F& Sun, 29 May 2022 07:49:40 +0100 FeedCreator 1.7.2 8b bytes, + formal verification throughout + dcache https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=209 <div><strong>Rev 209 - dgisselq</strong> (129 file(s) modified)</div><div>8b bytes, + formal verification throughout + dcache</div>+ /zipcpu/trunk/.gitignore<br />~ /zipcpu/trunk/bench/asm/Makefile<br />~ /zipcpu/trunk/bench/asm/zipdhry.S<br />~ /zipcpu/trunk/bench/cpp/helloworld.c<br />~ /zipcpu/trunk/bench/cpp/Makefile<br />+ /zipcpu/trunk/bench/cpp/README.md<br />+ /zipcpu/trunk/bench/formal<br />+ /zipcpu/trunk/bench/formal/.gitignore<br />+ /zipcpu/trunk/bench/formal/abs_div.v<br />+ /zipcpu/trunk/bench/formal/abs_mpy.v<br />+ /zipcpu/trunk/bench/formal/abs_prefetch.v<br />+ /zipcpu/trunk/bench/formal/busdelay.sby<br />+ /zipcpu/trunk/bench/formal/cpuops.sby<br />+ /zipcpu/trunk/bench/formal/dblfetch.sby<br />+ /zipcpu/trunk/bench/formal/dcache.gtkw<br />+ /zipcpu/trunk/bench/formal/dcache.sby<br />+ /zipcpu/trunk/bench/formal/div.gtkw<br />+ /zipcpu/trunk/bench/formal/div.sby<br />+ /zipcpu/trunk/bench/formal/f_idecode.v<br />+ /zipcpu/trunk/bench/formal/icontrol.sby<br />+ /zipcpu/trunk/bench/formal/idecode.gtkw<br />+ /zipcpu/trunk/bench/formal/idecode.sby<br />+ /zipcpu/trunk/bench/formal/Makefile<br />+ /zipcpu/trunk/bench/formal/mcve.sby<br />+ /zipcpu/trunk/bench/formal/mcve.v<br />+ /zipcpu/trunk/bench/formal/memops.sby<br />+ /zipcpu/trunk/bench/formal/pfcache.gtkw<br />+ /zipcpu/trunk/bench/formal/pfcache.sby<br />+ /zipcpu/trunk/bench/formal/pipemem.sby<br />+ /zipcpu/trunk/bench/formal/prefetch.sby<br />+ /zipcpu/trunk/bench/formal/wbdblpriarb.sby<br />+ /zipcpu/trunk/bench/formal/wbdmac.sby<br />+ /zipcpu/trunk/bench/formal/wbpriarbiter.sby<br />+ /zipcpu/trunk/bench/formal/wbwatchdog.sby<br />+ /zipcpu/trunk/bench/formal/zipcounter.sby<br />+ /zipcpu/trunk/bench/formal/zipcpu.gtkw<br />+ /zipcpu/trunk/bench/formal/zipcpu.sby<br />+ /zipcpu/trunk/bench/formal/zipjiffies.sby<br />+ /zipcpu/trunk/bench/formal/zipmmu.gtkw<br />+ /zipcpu/trunk/bench/formal/zipmmu.sby<br />+ /zipcpu/trunk/bench/formal/ziptimer.sby<br />+ /zipcpu/trunk/bench/rtl<br />+ /zipcpu/trunk/bench/rtl/Makefile<br />+ /zipcpu/trunk/bench/rtl/memdev.v<br />+ /zipcpu/trunk/bench/rtl/zipmmu_tb.v<br />+ /zipcpu/trunk/doc/.gitignore<br />+ /zipcpu/trunk/doc/gfx/.gitignore<br />~ /zipcpu/trunk/doc/gfx/cpu.dia<br />~ /zipcpu/trunk/doc/nextgen.html<br />~ /zipcpu/trunk/doc/orconf.pdf<br />+ /zipcpu/trunk/doc/orconf2017.pdf<br />+ /zipcpu/trunk/doc/orconf2018.pdf<br />~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br />~ /zipcpu/trunk/INSTALL.md<br />~ /zipcpu/trunk/Makefile<br />~ /zipcpu/trunk/README.md<br />~ /zipcpu/trunk/rtl/core<br />~ /zipcpu/trunk/rtl/core/cpuops.v<br />~ /zipcpu/trunk/rtl/core/dblfetch.v<br />~ /zipcpu/trunk/rtl/core/dcache.v<br />~ /zipcpu/trunk/rtl/core/div.v<br />~ /zipcpu/trunk/rtl/core/idecode.v<br />+ /zipcpu/trunk/rtl/core/iscachable.v<br />~ /zipcpu/trunk/rtl/core/memops.v<br />+ /zipcpu/trunk/rtl/core/mpyop.v<br />~ /zipcpu/trunk/rtl/core/pfcache.v<br />~ /zipcpu/trunk/rtl/core/pipefetch.v<br />~ /zipcpu/trunk/rtl/core/pipemem.v<br />~ /zipcpu/trunk/rtl/core/prefetch.v<br />+ /zipcpu/trunk/rtl/core/README.md<br />+ /zipcpu/trunk/rtl/core/slowmpy.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/cpudefs.v<br />+ /zipcpu/trunk/rtl/ex<br />+ /zipcpu/trunk/rtl/ex/busdelay.v<br />+ /zipcpu/trunk/rtl/ex/fwb_counter.v<br />+ /zipcpu/trunk/rtl/ex/fwb_master.v<br />+ /zipcpu/trunk/rtl/ex/fwb_slave.v<br />+ /zipcpu/trunk/rtl/ex/wbarbiter.v<br />+ /zipcpu/trunk/rtl/ex/wbdblpriarb.v<br />+ /zipcpu/trunk/rtl/ex/wbpriarbiter.v<br />~ /zipcpu/trunk/rtl/Makefile<br />~ /zipcpu/trunk/rtl/peripherals/icontrol.v<br />+ /zipcpu/trunk/rtl/peripherals/README.md<br />~ /zipcpu/trunk/rtl/peripherals/wbdmac.v<br />~ /zipcpu/trunk/rtl/peripherals/wbwatchdog.v<br />~ /zipcpu/trunk/rtl/peripherals/zipcounter.v<br />~ /zipcpu/trunk/rtl/peripherals/zipjiffies.v<br />~ /zipcpu/trunk/rtl/peripherals/zipmmu.v<br />~ /zipcpu/trunk/rtl/peripherals/ziptimer.v<br />+ /zipcpu/trunk/rtl/README.md<br />~ /zipcpu/trunk/rtl/zipbones.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br />~ /zipcpu/trunk/sim/cpp<br />~ /zipcpu/trunk/sim/cpp/Makefile<br />+ /zipcpu/trunk/sim/cpp/README.md<br />~ /zipcpu/trunk/sim/cpp/twoc.cpp<br />~ /zipcpu/trunk/sim/cpp/twoc.h<br />~ /zipcpu/trunk/sim/cpp/zipelf.cpp<br />~ /zipcpu/trunk/sim/cpp/zipelf.h<br />~ /zipcpu/trunk/sim/cpp/zsim.cpp<br />~ /zipcpu/trunk/sim/verilator<br />~ /zipcpu/trunk/sim/verilator/.gitignore<br />~ /zipcpu/trunk/sim/verilator/div_tb.cpp<br />~ /zipcpu/trunk/sim/verilator/Makefile<br />~ /zipcpu/trunk/sim/verilator/memsim.h<br />~ /zipcpu/trunk/sim/verilator/mpy_tb.cpp<br />~ /zipcpu/trunk/sim/verilator/pdump.cpp<br />~ /zipcpu/trunk/sim/verilator/pfcache_tb.cpp<br />+ /zipcpu/trunk/sim/verilator/README.md<br />~ /zipcpu/trunk/sim/verilator/testb.h<br />~ /zipcpu/trunk/sim/verilator/twoc.cpp<br />~ /zipcpu/trunk/sim/verilator/twoc.h<br />+ /zipcpu/trunk/sim/verilator/vversion.sh<br />+ /zipcpu/trunk/sim/verilator/zipcpu_tb.cpp<br />~ /zipcpu/trunk/sim/verilator/zipmmu_tb.cpp<br />~ /zipcpu/trunk/sw<br />~ /zipcpu/trunk/sw/.gitignore<br />~ /zipcpu/trunk/sw/gas-script.sh<br />~ /zipcpu/trunk/sw/gas-zippatch.patch<br />~ /zipcpu/trunk/sw/gcc-script.sh<br />~ /zipcpu/trunk/sw/gcc-zippatch.patch<br />~ /zipcpu/trunk/sw/Makefile<br />~ /zipcpu/trunk/sw/nlib-script.sh<br />~ /zipcpu/trunk/sw/nlib-zippatch.patch<br />+ /zipcpu/trunk/sw/README.md<br />~ /zipcpu/trunk/sw/zasm<br />~ /zipcpu/trunk/sw/zasm/.gitignore<br /> dgisselq Tue, 19 Mar 2019 03:24:12 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=209 Updating core to current/best version, to include dblfetch support and ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=205 <div><strong>Rev 205 - dgisselq</strong> (8 file(s) modified)</div><div>Updating core to current/best version, to include dblfetch support and ...</div>~ /zipcpu/trunk/rtl/core/cpuops.v<br />+ /zipcpu/trunk/rtl/core/dblfetch.v<br />~ /zipcpu/trunk/rtl/core/div.v<br />~ /zipcpu/trunk/rtl/core/idecode.v<br />~ /zipcpu/trunk/rtl/core/memops.v<br />~ /zipcpu/trunk/rtl/core/prefetch.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/cpudefs.v<br /> dgisselq Tue, 28 Mar 2017 15:26:49 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=205 RTL files for the 8-bit capable ZipCPU. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=201 <div><strong>Rev 201 - dgisselq</strong> (30 file(s) modified)</div><div>RTL files for the 8-bit capable ZipCPU.</div>~ /zipcpu/trunk/rtl<br />~ /zipcpu/trunk/rtl/aux/busdelay.v<br />~ /zipcpu/trunk/rtl/aux/wbarbiter.v<br />~ /zipcpu/trunk/rtl/aux/wbdblpriarb.v<br />~ /zipcpu/trunk/rtl/aux/wbpriarbiter.v<br />~ /zipcpu/trunk/rtl/core/cpuops.v<br />- /zipcpu/trunk/rtl/core/cpuops_deprecated.v<br />+ /zipcpu/trunk/rtl/core/dcache.v<br />~ /zipcpu/trunk/rtl/core/div.v<br />~ /zipcpu/trunk/rtl/core/idecode.v<br />- /zipcpu/trunk/rtl/core/idecode_deprecated.v<br />~ /zipcpu/trunk/rtl/core/memops.v<br />~ /zipcpu/trunk/rtl/core/pfcache.v<br />~ /zipcpu/trunk/rtl/core/pipefetch.v<br />~ /zipcpu/trunk/rtl/core/pipemem.v<br />~ /zipcpu/trunk/rtl/core/prefetch.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/cpudefs.v<br />~ /zipcpu/trunk/rtl/Makefile<br />~ /zipcpu/trunk/rtl/peripherals<br />~ /zipcpu/trunk/rtl/peripherals/flashcache.v<br />~ /zipcpu/trunk/rtl/peripherals/icontrol.v<br />~ /zipcpu/trunk/rtl/peripherals/wbdmac.v<br />~ /zipcpu/trunk/rtl/peripherals/wbwatchdog.v<br />~ /zipcpu/trunk/rtl/peripherals/zipcounter.v<br />~ /zipcpu/trunk/rtl/peripherals/zipjiffies.v<br />+ /zipcpu/trunk/rtl/peripherals/zipmmu.v<br />~ /zipcpu/trunk/rtl/peripherals/ziptimer.v<br />~ /zipcpu/trunk/rtl/zipbones.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br /> dgisselq Thu, 09 Mar 2017 18:08:47 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=201 Updated internal documentation. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=196 <div><strong>Rev 196 - dgisselq</strong> (1 file(s) modified)</div><div>Updated internal documentation.</div>~ /zipcpu/trunk/rtl/core/div.v<br /> dgisselq Thu, 03 Nov 2016 18:21:53 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=196 Cleaned up some parameters, trying to create more consistency. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=194 <div><strong>Rev 194 - dgisselq</strong> (3 file(s) modified)</div><div>Cleaned up some parameters, trying to create more consistency.</div>~ /zipcpu/trunk/rtl/core/pfcache.v<br />~ /zipcpu/trunk/rtl/core/pipemem.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br /> dgisselq Thu, 03 Nov 2016 18:20:42 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=194 These changes make it so the ALU multiplies pass a ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=193 <div><strong>Rev 193 - dgisselq</strong> (4 file(s) modified)</div><div>These changes make it so the ALU multiplies pass a ...</div>~ /zipcpu/trunk/rtl/core/cpuops.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/cpudefs.v<br />~ /zipcpu/trunk/rtl/Makefile<br /> dgisselq Thu, 03 Nov 2016 18:19:37 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=193 Lots of changes, most (all?) of them to the non-pipelined ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=179 <div><strong>Rev 179 - dgisselq</strong> (1 file(s) modified)</div><div>Lots of changes, most (all?) of them to the non-pipelined ...</div>~ /zipcpu/trunk/rtl/core/zipcpu.v<br /> dgisselq Thu, 15 Sep 2016 20:18:45 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=179 Rewrote the parameter controlled logic to be just that: perameter ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=178 <div><strong>Rev 178 - dgisselq</strong> (1 file(s) modified)</div><div>Rewrote the parameter controlled logic to be just that: perameter ...</div>~ /zipcpu/trunk/rtl/core/idecode.v<br /> dgisselq Thu, 15 Sep 2016 20:17:36 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=178 Fixed the illegal address logic to be more precise. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=177 <div><strong>Rev 177 - dgisselq</strong> (1 file(s) modified)</div><div>Fixed the illegal address logic to be more precise.</div>~ /zipcpu/trunk/rtl/core/pipefetch.v<br /> dgisselq Thu, 15 Sep 2016 20:14:26 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=177 Switched from distributed to block RAM, and adjusted the logic ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=176 <div><strong>Rev 176 - dgisselq</strong> (1 file(s) modified)</div><div>Switched from distributed to block RAM, and adjusted the logic ...</div>~ /zipcpu/trunk/rtl/core/pfcache.v<br /> dgisselq Thu, 15 Sep 2016 20:13:17 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=176 Fixed the carry bit for logical shifts: it is the ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=175 <div><strong>Rev 175 - dgisselq</strong> (1 file(s) modified)</div><div>Fixed the carry bit for logical shifts: it is the ...</div>~ /zipcpu/trunk/rtl/core/cpuops.v<br /> dgisselq Thu, 15 Sep 2016 20:10:53 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=175 Simplified the divide to improve timing performance. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=174 <div><strong>Rev 174 - dgisselq</strong> (1 file(s) modified)</div><div>Simplified the divide to improve timing performance.</div>~ /zipcpu/trunk/rtl/core/div.v<br /> dgisselq Thu, 15 Sep 2016 20:06:48 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=174 Logic updates, and bug fix corrections to bring this in ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=160 <div><strong>Rev 160 - dgisselq</strong> (8 file(s) modified)</div><div>Logic updates, and bug fix corrections to bring this in ...</div>~ /zipcpu/trunk/rtl/core/div.v<br />~ /zipcpu/trunk/rtl/core/idecode.v<br />~ /zipcpu/trunk/rtl/core/pipemem.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/peripherals/wbdmac.v<br />~ /zipcpu/trunk/rtl/peripherals/zipcounter.v<br />~ /zipcpu/trunk/rtl/peripherals/zipjiffies.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br /> dgisselq Wed, 15 Jun 2016 00:28:39 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=160 This fixes the pipelined memory problem that was introduced a ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=145 <div><strong>Rev 145 - dgisselq</strong> (1 file(s) modified)</div><div>This fixes the pipelined memory problem that was introduced a ...</div>~ /zipcpu/trunk/rtl/core/zipcpu.v<br /> dgisselq Fri, 13 May 2016 01:42:59 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=145 Minor changes, but fixes build of zippy_tb.cpp. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=140 <div><strong>Rev 140 - dgisselq</strong> (2 file(s) modified)</div><div>Minor changes, but fixes build of zippy_tb.cpp.</div>~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br />~ /zipcpu/trunk/rtl/core/idecode.v<br /> dgisselq Mon, 09 May 2016 12:19:09 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=140 This updates the CPU multiply instruction into a set of ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=138 <div><strong>Rev 138 - dgisselq</strong> (5 file(s) modified)</div><div>This updates the CPU multiply instruction into a set of ...</div>~ /zipcpu/trunk/rtl/core/cpuops.v<br />~ /zipcpu/trunk/rtl/core/idecode.v<br />~ /zipcpu/trunk/rtl/cpudefs.v<br />~ /zipcpu/trunk/sw/binutils-2.25.patch<br />~ /zipcpu/trunk/sw/gcc-zippatch.patch<br /> dgisselq Fri, 06 May 2016 14:54:30 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=138 Changes preceding an instruction set update, which will change the ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=133 <div><strong>Rev 133 - dgisselq</strong> (1 file(s) modified)</div><div>Changes preceding an instruction set update, which will change the ...</div>~ /zipcpu/trunk/rtl/core/cpuops.v<br /> dgisselq Fri, 22 Apr 2016 00:19:39 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=133 Lots of minor bug fixes. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=132 <div><strong>Rev 132 - dgisselq</strong> (1 file(s) modified)</div><div>Lots of minor bug fixes.</div>~ /zipcpu/trunk/rtl/core/zipcpu.v<br /> dgisselq Fri, 22 Apr 2016 00:17:59 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=132 Fixed a variable use before declaration error. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=131 <div><strong>Rev 131 - dgisselq</strong> (1 file(s) modified)</div><div>Fixed a variable use before declaration error.</div>~ /zipcpu/trunk/rtl/core/pipemem.v<br /> dgisselq Fri, 22 Apr 2016 00:13:00 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=131 Simplified the lock logic, and removed it when pipelining was ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=130 <div><strong>Rev 130 - dgisselq</strong> (1 file(s) modified)</div><div>Simplified the lock logic, and removed it when pipelining was ...</div>~ /zipcpu/trunk/rtl/core/idecode.v<br /> dgisselq Fri, 22 Apr 2016 00:12:28 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=130
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