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zipcpu WebSVN RSS feed - zipcpu https://opencores.org/websvn//websvn/listing?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2Fpipefetch.v& Thu, 28 Mar 2024 17:25:16 +0100 FeedCreator 1.7.2 8b bytes, + formal verification throughout + dcache https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=209 <div><strong>Rev 209 - dgisselq</strong> (129 file(s) modified)</div><div>8b bytes, + formal verification throughout + dcache</div>+ /zipcpu/trunk/.gitignore<br />~ /zipcpu/trunk/bench/asm/Makefile<br />~ /zipcpu/trunk/bench/asm/zipdhry.S<br />~ /zipcpu/trunk/bench/cpp/helloworld.c<br />~ /zipcpu/trunk/bench/cpp/Makefile<br />+ /zipcpu/trunk/bench/cpp/README.md<br />+ /zipcpu/trunk/bench/formal<br />+ /zipcpu/trunk/bench/formal/.gitignore<br />+ /zipcpu/trunk/bench/formal/abs_div.v<br />+ /zipcpu/trunk/bench/formal/abs_mpy.v<br />+ /zipcpu/trunk/bench/formal/abs_prefetch.v<br />+ /zipcpu/trunk/bench/formal/busdelay.sby<br />+ /zipcpu/trunk/bench/formal/cpuops.sby<br />+ /zipcpu/trunk/bench/formal/dblfetch.sby<br />+ /zipcpu/trunk/bench/formal/dcache.gtkw<br />+ /zipcpu/trunk/bench/formal/dcache.sby<br />+ /zipcpu/trunk/bench/formal/div.gtkw<br />+ /zipcpu/trunk/bench/formal/div.sby<br />+ /zipcpu/trunk/bench/formal/f_idecode.v<br />+ /zipcpu/trunk/bench/formal/icontrol.sby<br />+ /zipcpu/trunk/bench/formal/idecode.gtkw<br />+ /zipcpu/trunk/bench/formal/idecode.sby<br />+ /zipcpu/trunk/bench/formal/Makefile<br />+ /zipcpu/trunk/bench/formal/mcve.sby<br />+ /zipcpu/trunk/bench/formal/mcve.v<br />+ /zipcpu/trunk/bench/formal/memops.sby<br />+ /zipcpu/trunk/bench/formal/pfcache.gtkw<br />+ /zipcpu/trunk/bench/formal/pfcache.sby<br />+ /zipcpu/trunk/bench/formal/pipemem.sby<br />+ /zipcpu/trunk/bench/formal/prefetch.sby<br />+ /zipcpu/trunk/bench/formal/wbdblpriarb.sby<br />+ /zipcpu/trunk/bench/formal/wbdmac.sby<br />+ /zipcpu/trunk/bench/formal/wbpriarbiter.sby<br />+ /zipcpu/trunk/bench/formal/wbwatchdog.sby<br />+ /zipcpu/trunk/bench/formal/zipcounter.sby<br />+ /zipcpu/trunk/bench/formal/zipcpu.gtkw<br />+ /zipcpu/trunk/bench/formal/zipcpu.sby<br />+ /zipcpu/trunk/bench/formal/zipjiffies.sby<br />+ /zipcpu/trunk/bench/formal/zipmmu.gtkw<br />+ /zipcpu/trunk/bench/formal/zipmmu.sby<br />+ /zipcpu/trunk/bench/formal/ziptimer.sby<br />+ /zipcpu/trunk/bench/rtl<br />+ /zipcpu/trunk/bench/rtl/Makefile<br />+ /zipcpu/trunk/bench/rtl/memdev.v<br />+ /zipcpu/trunk/bench/rtl/zipmmu_tb.v<br />+ /zipcpu/trunk/doc/.gitignore<br />+ /zipcpu/trunk/doc/gfx/.gitignore<br />~ /zipcpu/trunk/doc/gfx/cpu.dia<br />~ /zipcpu/trunk/doc/nextgen.html<br />~ /zipcpu/trunk/doc/orconf.pdf<br />+ /zipcpu/trunk/doc/orconf2017.pdf<br />+ /zipcpu/trunk/doc/orconf2018.pdf<br />~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br />~ /zipcpu/trunk/INSTALL.md<br />~ /zipcpu/trunk/Makefile<br />~ /zipcpu/trunk/README.md<br />~ /zipcpu/trunk/rtl/core<br />~ /zipcpu/trunk/rtl/core/cpuops.v<br />~ /zipcpu/trunk/rtl/core/dblfetch.v<br />~ /zipcpu/trunk/rtl/core/dcache.v<br />~ /zipcpu/trunk/rtl/core/div.v<br />~ /zipcpu/trunk/rtl/core/idecode.v<br />+ /zipcpu/trunk/rtl/core/iscachable.v<br />~ /zipcpu/trunk/rtl/core/memops.v<br />+ /zipcpu/trunk/rtl/core/mpyop.v<br />~ /zipcpu/trunk/rtl/core/pfcache.v<br />~ /zipcpu/trunk/rtl/core/pipefetch.v<br />~ /zipcpu/trunk/rtl/core/pipemem.v<br />~ /zipcpu/trunk/rtl/core/prefetch.v<br />+ /zipcpu/trunk/rtl/core/README.md<br />+ /zipcpu/trunk/rtl/core/slowmpy.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/cpudefs.v<br />+ /zipcpu/trunk/rtl/ex<br />+ /zipcpu/trunk/rtl/ex/busdelay.v<br />+ /zipcpu/trunk/rtl/ex/fwb_counter.v<br />+ /zipcpu/trunk/rtl/ex/fwb_master.v<br />+ /zipcpu/trunk/rtl/ex/fwb_slave.v<br />+ /zipcpu/trunk/rtl/ex/wbarbiter.v<br />+ /zipcpu/trunk/rtl/ex/wbdblpriarb.v<br />+ /zipcpu/trunk/rtl/ex/wbpriarbiter.v<br />~ /zipcpu/trunk/rtl/Makefile<br />~ /zipcpu/trunk/rtl/peripherals/icontrol.v<br />+ /zipcpu/trunk/rtl/peripherals/README.md<br />~ /zipcpu/trunk/rtl/peripherals/wbdmac.v<br />~ /zipcpu/trunk/rtl/peripherals/wbwatchdog.v<br />~ /zipcpu/trunk/rtl/peripherals/zipcounter.v<br />~ /zipcpu/trunk/rtl/peripherals/zipjiffies.v<br />~ /zipcpu/trunk/rtl/peripherals/zipmmu.v<br />~ /zipcpu/trunk/rtl/peripherals/ziptimer.v<br />+ /zipcpu/trunk/rtl/README.md<br />~ /zipcpu/trunk/rtl/zipbones.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br />~ /zipcpu/trunk/sim/cpp<br />~ /zipcpu/trunk/sim/cpp/Makefile<br />+ /zipcpu/trunk/sim/cpp/README.md<br />~ /zipcpu/trunk/sim/cpp/twoc.cpp<br />~ /zipcpu/trunk/sim/cpp/twoc.h<br />~ /zipcpu/trunk/sim/cpp/zipelf.cpp<br />~ /zipcpu/trunk/sim/cpp/zipelf.h<br />~ /zipcpu/trunk/sim/cpp/zsim.cpp<br />~ /zipcpu/trunk/sim/verilator<br />~ /zipcpu/trunk/sim/verilator/.gitignore<br />~ /zipcpu/trunk/sim/verilator/div_tb.cpp<br />~ /zipcpu/trunk/sim/verilator/Makefile<br />~ /zipcpu/trunk/sim/verilator/memsim.h<br />~ /zipcpu/trunk/sim/verilator/mpy_tb.cpp<br />~ /zipcpu/trunk/sim/verilator/pdump.cpp<br />~ /zipcpu/trunk/sim/verilator/pfcache_tb.cpp<br />+ /zipcpu/trunk/sim/verilator/README.md<br />~ /zipcpu/trunk/sim/verilator/testb.h<br />~ /zipcpu/trunk/sim/verilator/twoc.cpp<br />~ /zipcpu/trunk/sim/verilator/twoc.h<br />+ /zipcpu/trunk/sim/verilator/vversion.sh<br />+ /zipcpu/trunk/sim/verilator/zipcpu_tb.cpp<br />~ /zipcpu/trunk/sim/verilator/zipmmu_tb.cpp<br />~ /zipcpu/trunk/sw<br />~ /zipcpu/trunk/sw/.gitignore<br />~ /zipcpu/trunk/sw/gas-script.sh<br />~ /zipcpu/trunk/sw/gas-zippatch.patch<br />~ /zipcpu/trunk/sw/gcc-script.sh<br />~ /zipcpu/trunk/sw/gcc-zippatch.patch<br />~ /zipcpu/trunk/sw/Makefile<br />~ /zipcpu/trunk/sw/nlib-script.sh<br />~ /zipcpu/trunk/sw/nlib-zippatch.patch<br />+ /zipcpu/trunk/sw/README.md<br />~ /zipcpu/trunk/sw/zasm<br />~ /zipcpu/trunk/sw/zasm/.gitignore<br /> dgisselq Tue, 19 Mar 2019 03:24:12 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=209 RTL files for the 8-bit capable ZipCPU. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=201 <div><strong>Rev 201 - dgisselq</strong> (30 file(s) modified)</div><div>RTL files for the 8-bit capable ZipCPU.</div>~ /zipcpu/trunk/rtl<br />~ /zipcpu/trunk/rtl/aux/busdelay.v<br />~ /zipcpu/trunk/rtl/aux/wbarbiter.v<br />~ /zipcpu/trunk/rtl/aux/wbdblpriarb.v<br />~ /zipcpu/trunk/rtl/aux/wbpriarbiter.v<br />~ /zipcpu/trunk/rtl/core/cpuops.v<br />- /zipcpu/trunk/rtl/core/cpuops_deprecated.v<br />+ /zipcpu/trunk/rtl/core/dcache.v<br />~ /zipcpu/trunk/rtl/core/div.v<br />~ /zipcpu/trunk/rtl/core/idecode.v<br />- /zipcpu/trunk/rtl/core/idecode_deprecated.v<br />~ /zipcpu/trunk/rtl/core/memops.v<br />~ /zipcpu/trunk/rtl/core/pfcache.v<br />~ /zipcpu/trunk/rtl/core/pipefetch.v<br />~ /zipcpu/trunk/rtl/core/pipemem.v<br />~ /zipcpu/trunk/rtl/core/prefetch.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/cpudefs.v<br />~ /zipcpu/trunk/rtl/Makefile<br />~ /zipcpu/trunk/rtl/peripherals<br />~ /zipcpu/trunk/rtl/peripherals/flashcache.v<br />~ /zipcpu/trunk/rtl/peripherals/icontrol.v<br />~ /zipcpu/trunk/rtl/peripherals/wbdmac.v<br />~ /zipcpu/trunk/rtl/peripherals/wbwatchdog.v<br />~ /zipcpu/trunk/rtl/peripherals/zipcounter.v<br />~ /zipcpu/trunk/rtl/peripherals/zipjiffies.v<br />+ /zipcpu/trunk/rtl/peripherals/zipmmu.v<br />~ /zipcpu/trunk/rtl/peripherals/ziptimer.v<br />~ /zipcpu/trunk/rtl/zipbones.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br /> dgisselq Thu, 09 Mar 2017 18:08:47 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=201 Fixed the illegal address logic to be more precise. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=177 <div><strong>Rev 177 - dgisselq</strong> (1 file(s) modified)</div><div>Fixed the illegal address logic to be more precise.</div>~ /zipcpu/trunk/rtl/core/pipefetch.v<br /> dgisselq Thu, 15 Sep 2016 20:14:26 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=177 This implements the &quot;new Instruction Set&quot; architecture for the Zip ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=69 <div><strong>Rev 69 - dgisselq</strong> (85 file(s) modified)</div><div>This implements the &quot;new Instruction Set&quot; architecture for the Zip ...</div>~ /zipcpu/trunk/bench/asm/helloworld.S<br />~ /zipcpu/trunk/bench/asm/ivec.S<br />~ /zipcpu/trunk/bench/asm/lodsto.S<br />~ /zipcpu/trunk/bench/asm/Makefile<br />~ /zipcpu/trunk/bench/asm/pcpc.S<br />~ /zipcpu/trunk/bench/asm/testdiv.S<br />~ /zipcpu/trunk/bench/asm/wdt.S<br />~ /zipcpu/trunk/bench/asm/zipdhry.S<br />~ /zipcpu/trunk/bench/cpp/Makefile<br />~ /zipcpu/trunk/bench/cpp/memsim.cpp<br />~ /zipcpu/trunk/bench/cpp/memsim.h<br />~ /zipcpu/trunk/bench/cpp/pdump.cpp<br />~ /zipcpu/trunk/bench/cpp/testb.h<br />~ /zipcpu/trunk/bench/cpp/twoc.cpp<br />~ /zipcpu/trunk/bench/cpp/twoc.h<br />~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br />~ /zipcpu/trunk/doc/gfx/bc.eps<br />~ /zipcpu/trunk/doc/gfx/bra.eps<br />~ /zipcpu/trunk/doc/gfx/cpu.dia<br />~ /zipcpu/trunk/doc/gfx/cpu.eps<br />~ /zipcpu/trunk/doc/gfx/cpu.png<br />~ /zipcpu/trunk/doc/gfx/memrd.eps<br />~ /zipcpu/trunk/doc/gfx/memwr.eps<br />~ /zipcpu/trunk/doc/gfx/regset.png<br />~ /zipcpu/trunk/doc/gfx/system.dia<br />~ /zipcpu/trunk/doc/gfx/system.eps<br />~ /zipcpu/trunk/doc/gfx/system.png<br />~ /zipcpu/trunk/doc/gfx/zipbones.dia<br />~ /zipcpu/trunk/doc/gfx/zipbones.png<br />~ /zipcpu/trunk/doc/iset.html<br />~ /zipcpu/trunk/doc/Makefile<br />~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br />~ /zipcpu/trunk/Makefile<br />~ /zipcpu/trunk/rtl/aux/busdelay.v<br />~ /zipcpu/trunk/rtl/aux/wbarbiter.v<br />~ /zipcpu/trunk/rtl/aux/wbdblpriarb.v<br />~ /zipcpu/trunk/rtl/aux/wbpriarbiter.v<br />~ /zipcpu/trunk/rtl/core/cpuops.v<br />+ /zipcpu/trunk/rtl/core/cpuops_deprecated.v<br />+ /zipcpu/trunk/rtl/core/div.v<br />+ /zipcpu/trunk/rtl/core/idecode.v<br />+ /zipcpu/trunk/rtl/core/idecode_deprecated.v<br />~ /zipcpu/trunk/rtl/core/memops.v<br />+ /zipcpu/trunk/rtl/core/pfcache.v<br />~ /zipcpu/trunk/rtl/core/pipefetch.v<br />~ /zipcpu/trunk/rtl/core/pipemem.v<br />~ /zipcpu/trunk/rtl/core/prefetch.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/cpudefs.v<br />~ /zipcpu/trunk/rtl/Makefile<br />~ /zipcpu/trunk/rtl/peripherals/flashcache.v<br />~ /zipcpu/trunk/rtl/peripherals/icontrol.v<br />~ /zipcpu/trunk/rtl/peripherals/wbdmac.v<br />+ /zipcpu/trunk/rtl/peripherals/wbwatchdog.v<br />~ /zipcpu/trunk/rtl/peripherals/zipcounter.v<br />~ /zipcpu/trunk/rtl/peripherals/zipjiffies.v<br />~ /zipcpu/trunk/rtl/peripherals/ziptimer.v<br />~ /zipcpu/trunk/rtl/peripherals/ziptrap.v<br />~ /zipcpu/trunk/rtl/zipbones.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br />~ /zipcpu/trunk/sw/lib/divs.S<br />~ /zipcpu/trunk/sw/lib/divu.S<br />~ /zipcpu/trunk/sw/lib/mpy32s.S<br />~ /zipcpu/trunk/sw/lib/mpy32u.S<br />~ /zipcpu/trunk/sw/zasm/asmdata.cpp<br />~ /zipcpu/trunk/sw/zasm/asmdata.h<br />~ /zipcpu/trunk/sw/zasm/Makefile<br />~ /zipcpu/trunk/sw/zasm/optest.cpp<br />~ /zipcpu/trunk/sw/zasm/sys.i<br />~ /zipcpu/trunk/sw/zasm/test.S<br />~ /zipcpu/trunk/sw/zasm/twoc.cpp<br />~ /zipcpu/trunk/sw/zasm/twoc.h<br />~ /zipcpu/trunk/sw/zasm/zasm.l<br />~ /zipcpu/trunk/sw/zasm/zasm.y<br />~ /zipcpu/trunk/sw/zasm/zdump.cpp<br />~ /zipcpu/trunk/sw/zasm/zopcodes.cpp<br />~ /zipcpu/trunk/sw/zasm/zopcodes.h<br />~ /zipcpu/trunk/sw/zasm/zparser.cpp<br />~ /zipcpu/trunk/sw/zasm/zparser.h<br />~ /zipcpu/trunk/sw/zasm/zpp.l<br />~ /zipcpu/trunk/sw/zipdbg/devbus.h<br />~ /zipcpu/trunk/sw/zipdbg/regdefs.h<br />~ /zipcpu/trunk/sw/zipdbg/zipdbg.cpp<br />+ /zipcpu/trunk/zip.vim<br /> dgisselq Tue, 22 Dec 2015 16:06:51 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=69 Simplified bus interactions, and added support for detecting illegal instructions (i.e. ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=63 <div><strong>Rev 63 - dgisselq</strong> (3 file(s) modified)</div><div>Simplified bus interactions, and added support for detecting illegal<br /> instructions (i.e. ...</div>~ /zipcpu/trunk/rtl/core/pipefetch.v<br />~ /zipcpu/trunk/rtl/core/pipemem.v<br />~ /zipcpu/trunk/rtl/core/prefetch.v<br /> dgisselq Thu, 22 Oct 2015 15:51:42 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=63 Here's a bit of work in progress for getting the ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=56 <div><strong>Rev 56 - dgisselq</strong> (10 file(s) modified)</div><div>Here's a bit of work in progress for getting the ...</div>~ /zipcpu/trunk/rtl/aux/wbpriarbiter.v<br />~ /zipcpu/trunk/rtl/core/cpuops.v<br />~ /zipcpu/trunk/rtl/core/pipefetch.v<br />~ /zipcpu/trunk/rtl/core/pipemem.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />+ /zipcpu/trunk/rtl/cpudefs.v<br />~ /zipcpu/trunk/rtl/Makefile<br />~ /zipcpu/trunk/rtl/peripherals/ziptimer.v<br />~ /zipcpu/trunk/rtl/zipbones.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br /> dgisselq Mon, 12 Oct 2015 13:26:05 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=56 Files added/updated to get Dhrystone benchmark to work. Several ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=48 <div><strong>Rev 48 - dgisselq</strong> (9 file(s) modified)</div><div>Files added/updated to get Dhrystone benchmark to work. Several ...</div>~ /zipcpu/trunk/rtl/core/memops.v<br />~ /zipcpu/trunk/rtl/core/pipefetch.v<br />- /zipcpu/trunk/rtl/core/pipemem.v<br />~ /zipcpu/trunk/rtl/core/prefetch.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/peripherals/wbdmac.v<br />- /zipcpu/trunk/rtl/peripherals/zipport.v<br />~ /zipcpu/trunk/rtl/zipbones.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br /> dgisselq Fri, 02 Oct 2015 21:48:41 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=48 A couple of quick updates: - The Zip CPU now supports ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=38 <div><strong>Rev 38 - dgisselq</strong> (6 file(s) modified)</div><div>A couple of quick updates:<br /> <br /> - The Zip CPU now supports ...</div>~ /zipcpu/trunk/rtl/core/pipefetch.v<br />+ /zipcpu/trunk/rtl/core/pipemem.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/Makefile<br />+ /zipcpu/trunk/rtl/zipbones.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br /> dgisselq Tue, 29 Sep 2015 16:38:09 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=38 *Lots* of changes to increase processing speed and remove pipeline ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=36 <div><strong>Rev 36 - dgisselq</strong> (34 file(s) modified)</div><div>*Lots* of changes to increase processing speed and remove pipeline ...</div>+ /zipcpu/trunk/bench/asm/lfsrleds.S<br />~ /zipcpu/trunk/bench/asm/lodsto.S<br />~ /zipcpu/trunk/bench/cpp/Makefile<br />~ /zipcpu/trunk/bench/cpp/memsim.cpp<br />~ /zipcpu/trunk/bench/cpp/memsim.h<br />~ /zipcpu/trunk/bench/cpp/testb.h<br />~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br />+ /zipcpu/trunk/doc/gfx/zippipe.dia<br />~ /zipcpu/trunk/doc/Makefile<br />~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br />~ /zipcpu/trunk/Makefile<br />~ /zipcpu/trunk/rtl/aux/busdelay.v<br />~ /zipcpu/trunk/rtl/aux/wbarbiter.v<br />+ /zipcpu/trunk/rtl/aux/wbdblpriarb.v<br />+ /zipcpu/trunk/rtl/aux/wbpriarbiter.v<br />~ /zipcpu/trunk/rtl/core/memops.v<br />~ /zipcpu/trunk/rtl/core/pipefetch.v<br />~ /zipcpu/trunk/rtl/core/prefetch.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/Makefile<br />+ /zipcpu/trunk/rtl/peripherals/wbdmac.v<br />+ /zipcpu/trunk/rtl/peripherals/zipport.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br />+ /zipcpu/trunk/sw/lib<br />+ /zipcpu/trunk/sw/lib/divs.S<br />+ /zipcpu/trunk/sw/lib/divu.S<br />+ /zipcpu/trunk/sw/lib/mpy32s.S<br />+ /zipcpu/trunk/sw/lib/mpy32u.S<br />~ /zipcpu/trunk/sw/zasm/asmdata.cpp<br />~ /zipcpu/trunk/sw/zasm/sys.i<br />~ /zipcpu/trunk/sw/zasm/test.S<br />~ /zipcpu/trunk/sw/zasm/zasm.y<br />~ /zipcpu/trunk/sw/zasm/zpp.l<br /> dgisselq Sun, 20 Sep 2015 13:09:46 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=36 A couple of changes: Registers can now be changed via ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=18 <div><strong>Rev 18 - dgisselq</strong> (4 file(s) modified)</div><div>A couple of changes: Registers can now be changed via ...</div>~ /zipcpu/trunk/rtl/core/pipefetch.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/Makefile<br />~ /zipcpu/trunk/rtl/zipsystem.v<br /> dgisselq Sun, 16 Aug 2015 00:59:04 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=18 This version works on an FPGA!!! (Or at least the wdt.S ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=11 <div><strong>Rev 11 - dgisselq</strong> (5 file(s) modified)</div><div>This version works on an FPGA!!!<br /> <br /> (Or at least the wdt.S ...</div>+ /zipcpu/trunk/bench/asm/lfsr.S<br />~ /zipcpu/trunk/bench/asm/wdt.S<br />~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br />~ /zipcpu/trunk/rtl/core/pipefetch.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br /> dgisselq Tue, 28 Jul 2015 11:53:26 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=11 Rebuilt the pipefetch (instruction fetch/cache module) so that it will let ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=3 <div><strong>Rev 3 - dgisselq</strong> (5 file(s) modified)</div><div>Rebuilt the pipefetch (instruction fetch/cache module) so that it will<br /> let ...</div>~ /zipcpu/trunk/rtl/core/cpuops.v<br />~ /zipcpu/trunk/rtl/core/memops.v<br />~ /zipcpu/trunk/rtl/core/pipefetch.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br /> dgisselq Mon, 27 Jul 2015 14:45:57 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=3 An initial load. No promises of what works or ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=2 <div><strong>Rev 2 - dgisselq</strong> (58 file(s) modified)</div><div>An initial load. No promises of what works or ...</div>+ /zipcpu/trunk/bench<br />+ /zipcpu/trunk/bench/asm<br />+ /zipcpu/trunk/bench/asm/ivec.S<br />+ /zipcpu/trunk/bench/asm/lodsto.S<br />+ /zipcpu/trunk/bench/asm/pcpc.S<br />+ /zipcpu/trunk/bench/cpp<br />+ /zipcpu/trunk/bench/cpp/Makefile<br />+ /zipcpu/trunk/bench/cpp/memsim.cpp<br />+ /zipcpu/trunk/bench/cpp/memsim.h<br />+ /zipcpu/trunk/bench/cpp/testb.h<br />+ /zipcpu/trunk/bench/cpp/twoc.cpp<br />+ /zipcpu/trunk/bench/cpp/twoc.h<br />+ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br />+ /zipcpu/trunk/doc<br />+ /zipcpu/trunk/doc/gfx<br />+ /zipcpu/trunk/doc/gfx/cpu.dia<br />+ /zipcpu/trunk/doc/gfx/cpu.eps<br />+ /zipcpu/trunk/doc/gfx/cpu.png<br />+ /zipcpu/trunk/doc/gfx/iset.html<br />+ /zipcpu/trunk/doc/gfx/system.dia<br />+ /zipcpu/trunk/doc/gfx/system.eps<br />+ /zipcpu/trunk/doc/gfx/system.png<br />+ /zipcpu/trunk/doc/gfx/topng.sh<br />+ /zipcpu/trunk/rtl<br />+ /zipcpu/trunk/rtl/aux<br />+ /zipcpu/trunk/rtl/aux/busdelay.v<br />+ /zipcpu/trunk/rtl/aux/wbarbiter.v<br />+ /zipcpu/trunk/rtl/core<br />+ /zipcpu/trunk/rtl/core/cpuops.v<br />+ /zipcpu/trunk/rtl/core/memops.v<br />+ /zipcpu/trunk/rtl/core/pipefetch.v<br />+ /zipcpu/trunk/rtl/core/prefetch.v<br />+ /zipcpu/trunk/rtl/core/zipcpu.v<br />+ /zipcpu/trunk/rtl/Makefile<br />+ /zipcpu/trunk/rtl/peripherals<br />+ /zipcpu/trunk/rtl/peripherals/flashcache.v<br />+ /zipcpu/trunk/rtl/peripherals/icontrol.v<br />+ /zipcpu/trunk/rtl/peripherals/zipcounter.v<br />+ /zipcpu/trunk/rtl/peripherals/zipjiffies.v<br />+ /zipcpu/trunk/rtl/peripherals/ziptimer.v<br />+ /zipcpu/trunk/rtl/peripherals/ziptrap.v<br />+ /zipcpu/trunk/rtl/zipsystem.v<br />+ /zipcpu/trunk/sw<br />+ /zipcpu/trunk/sw/zasm<br />+ /zipcpu/trunk/sw/zasm/Makefile<br />+ /zipcpu/trunk/sw/zasm/obj-pc<br />+ /zipcpu/trunk/sw/zasm/obj-pc/depends.txt<br />+ /zipcpu/trunk/sw/zasm/optest.cpp<br />+ /zipcpu/trunk/sw/zasm/tags<br />+ /zipcpu/trunk/sw/zasm/test.S<br />+ /zipcpu/trunk/sw/zasm/twoc.cpp<br />+ /zipcpu/trunk/sw/zasm/twoc.h<br />+ /zipcpu/trunk/sw/zasm/zasm.cpp<br />+ /zipcpu/trunk/sw/zasm/zdump.cpp<br />+ /zipcpu/trunk/sw/zasm/zopcodes.cpp<br />+ /zipcpu/trunk/sw/zasm/zopcodes.h<br />+ /zipcpu/trunk/sw/zasm/zparser.cpp<br />+ /zipcpu/trunk/sw/zasm/zparser.h<br /> dgisselq Sun, 26 Jul 2015 21:38:38 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Frtl%2Fcore%2F&rev=2
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