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Last updated projects We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) FIR-Gen   Updated on: 28-Aug-2008   VLM: 124 This programm generates synthesis able vhdl code from filter coefficients. The programm is written in C++.     M2G - Media Oriented Systems Transport (MOST) IP core   Updated on: 27-Aug-2008   VLM: 630 With the M2G protocol a high performance, very scalable and easy to implement multi media transport system for in car use shall be defined. Inspired by the MOST protocol (Media Oriented Systems Transport) (http://www.mostcooperation.com) but with...   Category :: Communication controller Language :: Verilog Language :: VHDL Standard :: Wishbone compliant core Development status :: Planning   Video compression systems   Updated on: 27-Aug-2008   VLM: 1872 The Video Systems project is a collection of readily available blocks to build different types of compression standards, like H.310, H.320, MPEG-1, MPEG-2 etc.   Category :: Video controller Development status :: Production/Stable   ZPU - the worlds smallest 32 bit CPU with GCC toolchain   Updated on: 26-Aug-2008   VLM: 3176 This is the worlds smallest 32 bit CPU with a GCC/GDB toolchain, operating systems support(eCos), simulator, etc. Multiple VHDL implementations available. BSD license, except for those pieces to the puzzle that already have another open so...   Category :: Microprocessor Language :: VHDL Phaze :: Design done Phaze :: FPGA proven Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   JOP: a Java Optimized Processor   Updated on: 25-Aug-2008   VLM: 1276 JOP is the implementation of the Java Virtual Machine (JVM) as concrete machine in hardware. The design is full synthesizable and fits in low-cost FPGA devices from Altera and Xilinx.   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   SD/MMC Controller   Updated on: 25-Aug-2008   VLM: 1071 SD (Secure Digital) and MMC memory card controller with Wishbone slave interface. Handles all aspects of card initialization, 512 byte block read, and block write. Hides the complicated SD/MMC memory interface, and presents the user with a simple...   Category :: Communication controller Language :: Verilog License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   Kotku - The IBM PC complete system   Updated on: 25-Aug-2008   VLM: 483 This project is connected with Zet, the FPGA port of the IA-32 processor.     USB 1.1 Host and Function IP core   Updated on: 25-Aug-2008   VLM: 2726 USB 1.1 host and function modes of operation. Full (12Mbps) and low speed (1.5Mbps) operation. Isochronous data transfers supported. Function mode supports four endpoints.   Category :: Communication controller Language :: Verilog License :: LGPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   VHDL wavefile package   Updated on: 24-Aug-2008   VLM: 127 This short and simple package makes it easy to read and write wave files for signal processing in simulations. This is usefull if you want to check your simulation results with Octave. There are no restrictions about the numbers of channels or...     a VHDL 8254 Timer   Updated on: 24-Aug-2008   VLM: 733 a VHDL timer, based upon the Intel 8254   Category :: Other Dependencies :: Other cores Language :: VHDL Phaze :: Design done Development status :: Production/Stable   Zet - An FPGA port of the IA-32 architecture   Updated on: 24-Aug-2008   VLM: 1008 This project implements a version of the common Intel IA-32 instruction set into a commercial FPGA.   Category :: Microprocessor Language :: Verilog License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Alpha   High Speed SDRAM Controller With Adaptive Bank Management and Command Pipeline   Updated on: 23-Aug-2008   VLM: 693 HSSDRC is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. The main features of HSSDRC IP core are: 1. Adaptive SDRAM bank control : command sequence is depending upon previous accesses to...   Category :: Memory core Language :: Other Phaze :: Design done Development status :: Alpha Development status :: Production/Stable   Plasma - most MIPS I(TM) opcodes   Updated on: 23-Aug-2008   VLM: 1794 The Plasma CPU core supports interrupts and all MIPS I(TM) user mode instructions except unaligned load and store operations.   Category :: Microprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   T400 µController   Updated on: 23-Aug-2008   VLM: 250 An implementation of National's COP400 4-bit microcontroller family architecture. It is intended to be used as a replacement for the original chip in SOCs recreating legacy systems.   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   csa   Updated on: 23-Aug-2008   VLM: 153 this is a core implement to a dvb csa, after reading the csa.c in vlc project, i decided try to implement it.