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EnSilica has further expanded its network of specialist design centers with the establishment of a new facility near Oxford (UK) focusing on RF and low power sensing applications. The new facility is headed by Alan Wong, formerly IC Design Director at Frontier Microsystems, and it extends EnSilica's skills-base addressing the needs of wireless connected IoT and wearable products.
EnSilica to provide BaySand’s customers with configurable eSi-RISC processor cores, eSi-Connect processor peripherals, eSi-Crypto encryption and eSi-Comms communications IP solutions as well hardware accelerators
EnSilica and Micrium have partnered to successfully port Micrium’s µC/OS-III® RTOS to EnSilica’s family of eSi-RISC processor cores. Micrium’s µC/OS-III is available on eSi-RISC with immediate effect.
EnSilica has launched the eSi-ECDSA cryptographic IP designed to help meet the high security communication and latency requirements of automotive Car2Car and Car2Infrastructure (Car2x) applications that form part of today’s emerging Intelligent Transport Systems.

is the openMSP430 on its way to SPACE ?
posted by Olivier, Girard on 31-Dec-2014
is the openMSP430 on its way to SPACE ?
First open-source Hybrid Memory Cube controller released
posted by Juri, Schmidt on 30-Sep-2014
openHMC - an open-source Hybrid Memory Cube Controller
ZTEX releases new Artix 7 FPGA Board with USB and DDR3 SDRAM
posted by Stefan, Ziegenbalg on 10-Apr-2014
ZTEX releases USB-FPGA Modules 2.13 with Artix 7 XC7A35T to XC7A100T FPGA, USB 2.0 controller, 256 MByte DDR3 SDRAM and on-board voltage regulators.
ZTEX releases a FPGA Board with largest Artix 7 FPGA
posted by Stefan, Ziegenbalg on 25-Nov-2013
ZTEX releases USB-FPGA Module 2.16 with Artix 7 XC7A200T FPGA, USB 2.0 Controller, on-board voltage regulators and many I/O's.
Abstract — A IDCT architecture is designed for

multistandard inverse transform. The proposed

architecture is used in multistandard decoder

of MPEG-2, MPEG-4 ASP, H.264/AVC and

VC-1. Two circuits share strategies, factor

share (FS) and adder share (AS), are applied

to the inverse transform architecture for saving

its circuit resource. Finally, the architecture is

extended as 2-D using registers as row to column

decomposition

Keywords — Circuit share, high-definition

video, multistandard inverse transform, multi-

standard, IDCT, reconfigurable architecture
open hardware survey
posted by Andres, Cicuttin on 21-May-2012
This is an invitation to participate to a survey on an open hardware initiative for sciintific purposes in line with UNESCO mission. The results will be share with all participants and will be used to raise awarnes of new ways of open collaboration and project sustainability in line with opencores' spirit.
Many thanks,
Andres Cicuttin,
Technical Assistant
ICTP (UNESCO-IAEA)
The Libre Software Meeting (LSM) is an annual event on free software taking place in july in France since 2000. The LSM meeting is organized this year in Geneva, Switzerland from 7th to 12th July. Amongst several tracks, the Libre Software Meeting will feature an « Embedded Systems and Open Hardware » track, for which the call for presentations has been released recently.
Migen, a Python toolbox for building complex digital hardware
posted by Sebastien, Bourdeauducq on 27-Jan-2012
The Milkymist project has started developing a new high level tool for the synthesis of complex digital systems.
DMAP, a company focused on high reliability semiconductor applications and producing DO-254 compliant IP, has made available to the market PCI Express and Ethernet (Gigabit, 10G) IP for DO-254 applications that has been verified using SystemVerilog and Assertion Based Verification (ABV) in an OVM environment.
The NEW OpenRISC FPGA development board is now released
posted by Marcus, Erlandsson on 22-Nov-2011
The new OpenRISC-FPGA-development board is now released and it's specially designed to match OpenRISC processor SoC designs. The board supports the most common/wanted interfaces, with a small physical size and easy connections/debugging solution. We offer this powerful board as a low-cost FPGA development board, back to the community.
Sigasi Starter Edition, Forever Free
posted by Philippe, Faes on 01-Jul-2011
Sigasi launched a Starter Edition of its VHDL design environment. The starter edition will be permanently free of charge. If your project is small enough (and dozens of OpenCores projects are) you even get the full functionality of the Pro version.
New Book: 100 Power Tips for FPGA Designers
posted by evgeni, stavinov on 30-Jun-2011
Now available in paperback and e-book formats, “100 Power Tips for FPGA Designers” book is a collection of short articles on various aspects of FPGA design: synthesis, simulation, porting ASIC designs, floorplanning and timing closure, design methodologies, design optimizations, RTL coding, IP core selection, and many others.
In this article, we suggest to build on-die switched-capacitor voltage regulators to significantly reduce the power consumption of the OpenRISC SoCs while maintaining performance. We hope to gain your feedback to better understand the SoCs voltage regulators' needs.
After years of passionate and engaging development, the video synthesizer from the Milkymist project, with open source IP, is expected to go out of beta in August.
UK OSHUG to cover OpenCores and OpenRISC
posted by OpenCores, Admin on 07-Apr-2011
The next meeting of the Open Source Hardware Users Group (OSHUG) will include a talk (by me) on OpenCores and OpenRISC. The meeting on the evening of 21 April will also include an Introduction to Programmable Logic and a talk on using FPGAs for Computer Conservation.

Attendance is free and full details can be found at:
http://oshug.org/event/9
theora encoder core
posted by Vasiliy, Vasilievich on 16-Mar-2011
looking for interested for creating open theora encoder core. If you are interested e-mail me.
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