openMSP430

The implemented hardware multiplier executes 16x16 multiplication correctly. The TI implementation of 16x8 and 8x8 multiplation automaticlly zeros the upper byte during a byte move operation to OP1 or OP2 registers. The currently implemented hardware multiplier does not zero the upper byte.

The problem occurs using IARs floating point library multiplcation and the printf %f routines with the hardware multiplier option enabled.

For reference, see TI's slaa02 page 7: "Notice that input registers Operand1 and Operand2 behave like CPU registers, where the high-register byte is cleared if the register is modified by a byte instruction. This simplifies the use of 8-bit operands."

Mark.

Thanks for reporting this Mark. This bug is now fixed with SVN version 186.

Hi, I need verilog code for finite field multipliers

can someone share a verilog code for n-bit multiplier which is using ripple carry ader??