RD' and WR' not asserted for INS A, BUS and OUTL BUS, A
Information:
Type :: BUG
Status :: CLOSED
Assigned to ::
Arnim, Laeuger
Description:
Affected releases: 0.1 BETA, 0.2 BETA, 0.3 BETA, 0.4 BETA
The control signals RD' and WR' are not asserted when the instructions INS A, BUS and OUTL BUS, A are executed. The BUS is read or written but the control signals are missing.
Fixed in:
decoder.vhd 1.16
Fix will be included in next release.
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