ethenet at 100Mbps :: Bugtracker

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ethenet at 100Mbps

Information:
Type :: REQUEST
Status :: OPENED
Assigned to :: nobody

Description:
Hi,

i made an attempt to setup ethernet link at 100Mbps by changing register 0
bit 13 in SMI (LAN83C185 datasheet p34) init sequence in ethernet.c

EthernetInit :
unsigned long data=0x5F802100; //SMI R0 = 100Mbps full duplex

RX and TX_CLK are then clocked at 25Mhz instead of 2.5Mhz
but can't figure out what should be updated in eth_dma.vhd

Any hilight appreciated

Thanks & Regards
OR

Comments:

Weinrich, Matthias	Jun 4, 2010
.... there seems a lot more to do than just configure the PHY accordingly. The Ethernet TX and RX clock change to 25Mhz as you mentioned. Their edges are detected by the system clock which is 25Mhz too, so there is no way to make that work reliable until the system clock is at least 3 times higher. So far my understanding of the core is that this would be quite a task.... A FIFO introduced in the ethernet controller may bridge the gap between the two clock domains but again that will turn out to be a lot of work and make the design more specific to match a particular target device (Xilinx, Altera,....). Matthias

Weinrich, Matthias

Jun 4, 2010

.... there seems a lot more to do than just configure the PHY accordingly. The Ethernet TX and RX clock change to 25Mhz as you mentioned. Their edges are detected by the system clock which is 25Mhz too, so there is no way to make that work reliable until the system clock is at least 3 times higher. So far my understanding of the core is that this would be quite a task.... A FIFO introduced in the ethernet controller may bridge the gap between the two clock domains but again that will turn out to be a lot of work and make the design more specific to match a particular target device (Xilinx, Altera,....).

Matthias

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