Amber ARM-compatible core

We use the a23 with Cache enabled. While executing a push {r3,lr}, the processor stalls forever while writing the second register (lr). I debugged this issue and found the following:

Due to a weird coincidence, the wb_stall and cache_stall together create a three cycle high o_fetch_stall signal in our design. The cache_stall is high the first cycle, the wb_Stall the second and third. This prevents data_access_update in execute.v to get high. After three cycles, the SAME write transaction is completely restarted, making the cache_stall high the first cycle, and the wb_stall the second and third. As a result, the core stalls forever, continuously writing the lr register.

I think it is incorrect that the write transaction is restarted. The core does get an acknowledgement from the bus. How can a write transaction restart when the stalling lines are high ?

Can you create a short assembly test that recreates the bug?

I am seeing the same issue with the a23 core with cache enabled. I'm simply running a very basic 'hello world' test written in C, using the Sorcery Codebench Lite toolchain.

The 'push {fp, lr}' is the first instruction in main(), and causes an endless loop of writes to memory.

Please sent me the assembly and I will debug it.

Unable to reproduce. Closing the bug.