RTL Design Engineer
Information:
Type :: REQUEST
Status :: OPENED
Assigned to ::
Description:
When RX FIFO FULL signal goes true, the MAC_rx_Ctrl state machine aborts receiving the frame, as it should.
However, the MAC_rx_FIFO.v logic was changed recently to assert Fifo_full up to 4 words earlier using a new signal called Almost_Full.
This has two drawbacks:
1) FIFO space is wasted. This is particularly troublesome when the minimum FIFO length (32) is used.
2) Almost_full does not appear to beneficially prevent a packet from being lost since its assertion causes an abort.
I recommend removing the Almost_Full logic and using original logic ("Full") instead. This allows the entire FIFO to be utilized.
Comments:
No comments yet...
Post a comment:
Login to post comments!