Hi,

I have recently written a population count core. It returns the number of '1' bits in an input word, e.g. an input of "11101010" would return 5.

The width is generic, and can be set to anything. Pipelining is configurable too.

Whilst this is already a "solved problem" - just google for Wallace tree to see what I mean - I haven't seen any free cores that simultaneously give good performance in recent FPGAs, have a generic width and have a thorough test bench.

Post-PAR Performance in virtex 6 (-1 speed grade)
512 bit input : 585 LUTs, 5.271 ns clock period
256 bit input : 325 LUTs, 5.099 ns clock period
128 bit input : 165 LUTs, 2.719 ns clock period
64 bit input : 68 LUTs, 2.209 ns clock period
32 bit input : 39 LUTs, 1.622 ns clock period

It ought to be possible to reduce the clock period with wider inputs given some twiddling of pipeline stages. (It's already fast enough for my application.)

The body that I'm doing this work for has kindly allowed me to release it to the public domain.

Here's the question: should I post this on opencores? Would anyone be interested?

Cheers,
Allan

Yes you can share if you can, coz there are many ways to implement this bit count and it is always good to have other implementation to benchmark against ... Few academic papaers also use DSP slice for it ... with good timing too.