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All forums Cores Generic memory verilog files: (generic_spram.v and generic_dpram.v verilog files) deleted
All forums Cores Generic memory verilog files: (generic_spram.v and generic_dpram.v verilog files) deleted 
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Generic memory verilog files: (generic_spram.v and generic_dpram.v verilog files) deleted
by patrick on Jul 7, 2010 |
patrick
Posts: 1 Joined: Feb 20, 2006 Last seen: Dec 30, 2010 |
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Dear Administrator of Opencores,
The files which are used by the project "minirisc" are removed in Opencores.org.
Could you send me the verilog files?
About the project "minrisc" of Opencores, I cannot find out the synthesizable verilog files for the instances called as spram and dpram.
These files are declared in ./minirisc/trunk/sim/run (last two files)
ncverilog \
... \
../../generic_memories/rtl/verilog/generic_spram.v \
../../generic_memories/rtl/verilog/generic_dpram.v
Please also find the reply from the author of project "minirisc" below.
Regards,
Patrick
---------- Forwarded message ----------
From: Rudolf Usselmann
Date: 2010/7/7
Subject: Re: Generic memory verilog files: (generic_spram.v and generic_dpram.v verilog files)
To: Patrick
On Wed, 2010-07-07 at 16:05 +0800, Patrick Yip wrote:
> Dear Rudolf Usselma,
>
> Thank you for your reply.
>
> I am sorry to say that these files are not located in the project
> directory originally as shown in your "run" file. They are your
> generic memory files (file names: generic_dpram.v and generic_spram.v)
>
> Please find the path of the verilog files below. The "run" file is
> also attached.
>
> When I tried to run sythesis, it fails to locate these verilog
> modules. Might you send these verilog files to me? (generic memory
> files) Thank you very much.
>
> In NC-verilog "run" file:
> .....
> ../verilog/core/register_file.v \
> \
> ../../generic_memories/rtl/verilog/generic_spram.v \
> ../../generic_memories/rtl/verilog/generic_dpram.v
>
>
> Best wishes,
>
> Patrick
These files are NOT part of the MiniRisc project.
CHECK WITH OPENCORES Administrators where the project holding
those files went !
rudi
=============================================================
Rudolf Usselmann, ASICS World Services, http://www.asics.ws
Your IP Partner: USB, SATA, ATA, SD/MMC/SDIO, GPON, FEC, etc.
Now shipping USB 3.0 Device IP Core !
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cost has been forgotten". - Unknown.
run (0 kb)
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RE: Generic memory verilog files: (generic_spram.v and generic_dpram.v verilog files) deleted
by johnsconley on Jul 30, 2010 |
johnsconley
Posts: 1 Joined: Jan 7, 2009 Last seen: Dec 2, 2010 |
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what can we do with this Xilinx error!
ERROR:HDLCompilers:87 - "../oc8051_ram_256x8_two_bist.v" line 132 Could not find module/primitive 'generic_dpram' Can you help please John |
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RE: Generic memory verilog files: (generic_spram.v and generic_dpram.v verilog files) deleted
by yildiza on Jul 30, 2010 |
yildiza
Posts: 2 Joined: Oct 29, 2009 Last seen: Apr 12, 2011 |
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I think you should go to unisim library in Xilinx folder. You should search the Xilinx primitive source files and find the updated/actual version of your file.
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RE: Generic memory verilog files: (generic_spram.v and generic_dpram.v verilog files) deleted
by yannv on Feb 26, 2011 |
yannv
Posts: 11 Joined: Feb 6, 2009 Last seen: Feb 7, 2012 |
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At least generic_dpram is in svn module common (svn co http://opencores.org/ocsvn/common/common/trunk common). I'm not sure where in the project hierarchy common might be found (if at all), nor where the spram model is. I found mention of common in the coding guidelines at http://cdn.opencores.org/downloads/
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