Hello! I want to simulate amber23 core in modelsim se plus 5.7.. I never simulated any core before therefore kindly guide me from the scratch how to simulate amber 23 core.Any help would be appreciated.

Generally speaking, you need to invoke Modelsim and then add all the files from amber/trunk/hw/vlog/tb and amber/trunk/hw/amber23. The testbench should be the "top" of the design, and it should "instantiate" the "core" of the design. You will have to study the files in folder "tb" to see if that's how they are intended to be used.

Sidebar: When you say first that you "have never simulated any core before," and then you say that you want to start with Amber23, wouldn't you agree that is similar to saying that you have never flown an airplane, but you want to start by flying a jumbo jet? Why not use a more simple core to learn Modelsim and how to simulate a core?

Also, please note that there are instructions in the Amber documentation on how to use the Xilinx simulator. The xilinx simulator "isim" is not the same as the Modelsim simulator, but it will give you a good start on how simulation works in the general sense. Take a look at page 7 of the Amber Project User Guide and it will tell you about running simulations. Why don't you try following that simulation guide first, and then you will be more informed regarding simulation before running Modelsim.

Also, please note that when you download the free Xilinx webpack tools, you can also download a free Xilinx version of Modelsim. So if you first follow the Amber documentation for "isim" then as the next step you should be able to convert and translate those instructions and perform the similar flow in Modelsim.

I hope that helps.

Hi,
I know this might not be the right place for this question but I'm trying to synthesize the amber core using DC.
I am using DC 2013 which apparently doesn't understand Verilog 2001 constructs. Has anyone else ran into this error? If yes, please let me know if you found any work-aroud for this.

Thanks!
Sanjay

what errors does DC reporting??

Hi, I want to implement the amber23 core on Spartan 6, SP-605.

Therefore, I use the ISE 14.5 webpack version.

The user guide said it can be implemented. I implemented the amber23

and set the top module as 'system.v' and open all sources in the hw/vlog,

but the compile result is

INTERNAL_ERROR:Xst:cmain.c:3423:1.29 - Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.

Therefore, search about this error, and change the process properties like

opt_mode, opt_level, keep-hierarchy, read_cores, use_dsp48, equivalent register removal,
-use_new_parser yes ...

but it doesn't work...

and remove related with the ddr3.v, because I don't need it and there's no file about ddr3.v in amber prj, but the error was not dissapear...

Please help me to implement the prj

or if you have the ISE project file that you already done by the a23 core, please talk to me

Thank you

What software tools were used to create the Amber core PDF documents (i.e. 'amber-core.pdf')? I am particularly interested in how the diagrams were created - I am impressed by the quality of these diagrams. And I have found creating block diagrams of processor implementations to be challenging.

Hello.

I'm trying to use amber23 core.

But there is no information about memory map and linker script.

I'm really digging to operate interrupt in amber23 core.

If you guys succeed on interrupt, please give me some advice.

Thanks.
Dave

GCC are dropping support for older ARMs, according to their changelog https://gcc.gnu.org/gcc-6/changes.html#arm

This means that Amber will not be supported by GCC anymore.

I am using Amber-25 and I have some problems with the Link Register ( lr ).

My first thought is that I have not initialized appropriately the system in BOOT.s start file.
I want some good and complete example of that file or a guidance like the sources in sw/ amber directory.



Description of my problem:

Let's assume that Program Counter register ( PC )
has the value of 0x00000030 at some point, and at that point, we execute a
branch instruction " bl Addres " , the " lr " register should take the value of
"new lr=0x00000034".The problem is that instead of the expected address it sets to
" new lr=0x20000034 ". This problem does not occur at some "random" point
not necessary at every bl instruction.

Did anyone try to add reset for this core? It's pretty strange to have CPU which cannot be restarted. There is a good Archimedes emulator in FPGA but you cannot reset this computer because there is no reset signal in CPU..

Does anybody try to synthesize Amber25 Core in synthesizer tool? Where to find SDC for the core?

How to synthesize amber core in DC? It is giving errors.