I try to design CIC decimator in Matlab, then implementing to FPGA. When running simulation in Matlab, it can work with frequency domain as can be seen in attachment file. However, when the code is converted to HDL code, it can work only for the 1st and 2nd stage, the 3rd stage has no signal. Thus, the final output has no signal. Could anyone have experience on this topic, please help? Thanks in advance.