Has the requiring of some bits of page coloring (either for all aliasing virtual addresses or all addresses) been considered? Universal page coloring could make a skewed associative L1 cache more powerful, allow fewer bits in TLBs, allow initializing (part of) the cache tag comparison earlier, and allow larger data caches without higher associativity or snooping on misses (this last is avoided by coloring only aliases and need not apply to Icaches [only {rare} invalidations would need to snoop in a virtually-indexed Icache], but coloring would allow avoiding a few tag bits in such cases). Universal page coloring also allows software to act against conflict misses in a physically indexed lower-level cache (and tends to avoid conflicts in the common case of sequential virtual page activity). (With added complexity, one could have modes for page coloring such that a non-colored mode would have a smaller physical address space and might have to snoop on misses. One could also detect non-coloring in hardware and set a bit that indicates snooping is required [though a page-coloring system would not be able to benefit from a larger physical address space].) Paul A. Clayton -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums/openrisc/attachments/20040921/4f685c4d/attachment.htm