Hi everyone,

did anyone thought about a DDR2 controller with wishbone interface yet?

Maybe some DDR2 controller could be adapted to get a wishbone interface or a DDR one with wishbone could be extended to DDR2 (as far as it is even possible).

But as far as I have seen, there is no open DDR2 core available. Here are the opencores projects related to this topic:

-I have seen that the wb_ddr project is a wishbone interfaced DDR controller, which is already marked as stable.

-The orpsoc implementation seems to use a custom wishbone SDRAM controller.

-The versatile_mem_ctrl is from the same maintener of the SDRAM controller from the orpsoc. Is is still said to be in planing phase. Yet, the idea is to have a wishbone interface, Dual async FIFO buffers and a set of specific memory controllers. Maybe SDRAM is about to be ready but not yet, I don't know. There is though the SDRAM controller being used by the orpsocv2.

-The hpdmc is stable, is a DDR controller and use an interface called FML. They say, they have tested it using a WISHBONE/FML bridge, which sounds to be available but I couldn't find.

-The hssdrc project is a SDRAM controller, but they intend to create a wishbone interface for it and to create DDR and DDR2 controllers based on it. Though they are in alpha state and seem not yet to have tested in real hardware.

Possibilities:
-Probably the easiest way to go, would be to adapt the wb_ddr controller to DDR2.
-work with the versatile_mem_ctrl, since it also has this goal.
-adapt the hpdmc DDR controller to DDR2 and find the wishbone/FML bridge.

Bottom line:
-it seems that there are many projects aiming the same. Maybe they could cooperate or get feedback from done parts from the other projects.

Questions.
-Is it possible to extend a DDR controller to DDR2? How hard?
-Is there any DDR2 controller open core? If yes, maybe a done wishbone bridge could communicate to it?

Thanks in advance,
Raul

Hi all,

Thanks, Raul, for starting this important topic. We are also looking for DDR2 Wishbone controller (for use with Spartan 3a 1800 board) and looks like currently there is no working implementations available.

GRLIB IP Library has a stable DDR2 controller licensed under GPL. It uses AMBA however. Maybe it could be used together with Wishbone/AMBA bridge or can be a good start for creating a new Wishbone DDR2 controller. I didn't yet look into the code deeply however.

Any comments on this subject will be greatly appreciated.

Regards,
Andrey

Hi all,

the versatile_mem_ctrl is as of this time of writing functions in simulator and hardware testing is planned for the next step. Current implementation supports SDR SDRAM but the nature of the implementation is in such a way that enabling support for different memory types is easily achieved.

Short presentation of the structure of versatile_mem_ctrl:
Design is built up from three different blocks
1. wishbone interface with up to 8 wishbone ports working in parallel
2. 8 command and data FIFOs to memory
8 data FIFO with read data from memories
3. FSM for memory control

The wishbone interface monitors traffic on the ports and fills FIFO channels with command and data going to the memories. The FSM on the other side of the FIFOs will execute the commands.

The FIFO implementation is asynchronous meaning that wishbone clock and sdram clock are independent.

To get DDR2 support the following should be updated:
FSM with memory control

Since the FIFOs are async the new FSM can be run at a higher speed offered by DDR memories.

Conclusion:
DDR support is planned however implementation will go faster if more resources are involved. Feel free to join the project!!!

Hi,
I am new to opencores.org. My interests are to understand OR1200 CPU architecture. Currently I am spending time looking at OR1200 verilog code. Rather than just understanding code I thought getting involved in a project is more useful. I am interested in DDR2 controller project and need some guidance on how to get started.
I will be waiting for replies

-Praveen

Hi! As I can see trunk of versatile_mem_ctrl is 62 days old. Is anyone working on it? Is anybody still interested in DDR2 backend for this controller? I'd like to use such a "beast" on my Xilix 1800 board but I'm to lazy to write backand by myself. :)

This bridge is available at milkymist.org - I just did not find time to put and maintain a copy at OpenCores. If your system is entirely based on Wishbone, you'll need a CSR bridge as well; also available in Milkymist.

Using HPDMC with 16-bit DDR2 should be fairly straightforward. You basically need to:
- make the I/O go twice as fast (i.e. replace the IDDR and ODDR blocks by some stuff that samples 4 times during a clock period; on Virtex you can try ISERDES and OSERDES)
- on the software side, adapt the memory initialization sequence to DDR2

If you need assistance I'm willing to help and I'll be happy to hear about your successes or problems with DDR2. E-mail sebastien dot bourdeauducq at lekernel dot net.