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minsoc: Starting CPU error

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minsoc: Starting CPU error by jb007 on Aug 12, 2010			jb007 Posts: 29 Joined: May 3, 2009 Last seen: Jun 29, 2020
Hi All, I've had minsoc running under cygwin and windows 7 with no problems except for cygwin seems very slow. So I'm now trying same under ubuntu lucid 10.04. I get the following: jb@xpc:~/minsoc/sim/run$ ./start_server Enumerating JTAG chain... Devices on JTAG chain: Index Name ID Code IR Length ---------------------------------------------------------------- 0: (unknown) 0x149511C3 -1 Target device 0, JTAG ID = 0x149511c3 Using command-line debug command 0x8 * Doing self-test * Stall or1k - CPU(s) stalled. SRAM test: expected 11112222, read 11112222 expected 33334444, read 33334444 expected 55556666, read 55556666 expected 77778888, read 77778888 expected 9999aaaa, read 9999aaaa expected bbbbcccc, read bbbbcccc expected ddddeeee, read ddddeeee expected ffff0000, read ffff0000 expected dedababa, read dedababa SRAM test passed Testing CPU0 (or1k) - writing instructions Setting up CPU0 Starting CPU0! Read npc = 00000010 ppc = 00000028 r1 = 00000005 Expected npc = 00000010 ppc = 00000028 r1 = 00000005 Read npc = 00000028 ppc = 00000028 r1 = 00000008 Expected npc = 00000010 ppc = 00000028 r1 = 00000008 Read npc = 00000024 ppc = 00000020 r1 = 0000000b Expected npc = 00000028 ppc = 00000024 r1 = 0000000b Read npc = 00000020 ppc = 00000020 r1 = 00000018 Expected npc = 00000024 ppc = 00000020 r1 = 00000018 Read npc = 0000001c ppc = 00000018 r1 = 00000031 Expected npc = 00000020 ppc = 0000001c r1 = 00000031 Read npc = 00000020 ppc = 0000001c r1 = 00000032 Expected npc = 00000024 ppc = 00000020 r1 = 00000032 Read npc = 00000010 ppc = 00000028 r1 = 00000063 Expected npc = 00000014 ppc = 00000010 r1 = 00000063 Read npc = 00000010 ppc = 00000028 r1 = 00000063 Expected npc = 00000028 ppc = 00000024 r1 = 00000065 Read npc = 00000010 ppc = 00000028 r1 = 00000094 Expected npc = 00000010 ppc = 00000028 r1 = 000000c9 result = deaddef0 Self-test FAILED * Bailing out! jb@xpc:~/minsoc/sim/run$ Any ideas as to why it's not getting the right values when it reads the CPU regs? Jim Hi All, I've had minsoc running under cygwin and windows 7 with no problems except for cygwin seems very slow. So I'm now trying same under ubuntu lucid 10.04. I get the following: jb@xpc:~/minsoc/sim/run$ ./start_server Enumerating JTAG chain... Devices on JTAG chain: Index Name ID Code IR Length ---------------------------------------------------------------- 0: (unknown) 0x149511C3 -1 Target device 0, JTAG ID = 0x149511c3 Using command-line debug command 0x8 * Doing self-test * Stall or1k - CPU(s) stalled. SRAM test: expected 11112222, read 11112222 expected 33334444, read 33334444 expected 55556666, read 55556666 expected 77778888, read 77778888 expected 9999aaaa, read 9999aaaa expected bbbbcccc, read bbbbcccc expected ddddeeee, read ddddeeee expected ffff0000, read ffff0000 expected dedababa, read dedababa SRAM test passed Testing CPU0 (or1k) - writing instructions Setting up CPU0 Starting CPU0! Read npc = 00000010 ppc = 00000028 r1 = 00000005 Expected npc = 00000010 ppc = 00000028 r1 = 00000005 Read npc = 00000028 ppc = 00000028 r1 = 00000008 Expected npc = 00000010 ppc = 00000028 r1 = 00000008 Read npc = 00000024 ppc = 00000020 r1 = 0000000b Expected npc = 00000028 ppc = 00000024 r1 = 0000000b Read npc = 00000020 ppc = 00000020 r1 = 00000018 Expected npc = 00000024 ppc = 00000020 r1 = 00000018 Read npc = 0000001c ppc = 00000018 r1 = 00000031 Expected npc = 00000020 ppc = 0000001c r1 = 00000031 Read npc = 00000020 ppc = 0000001c r1 = 00000032 Expected npc = 00000024 ppc = 00000020 r1 = 00000032 Read npc = 00000010 ppc = 00000028 r1 = 00000063 Expected npc = 00000014 ppc = 00000010 r1 = 00000063 Read npc = 00000010 ppc = 00000028 r1 = 00000063 Expected npc = 00000028 ppc = 00000024 r1 = 00000065 Read npc = 00000010 ppc = 00000028 r1 = 00000094 Expected npc = 00000010 ppc = 00000028 r1 = 000000c9 result = deaddef0 Self-test FAILED * Bailing out! jb@xpc:~/minsoc/sim/run$ Any ideas as to why it's not getting the right values when it reads the CPU regs? Jim

RE: minsoc: Starting CPU error by rfajardo on Aug 12, 2010			rfajardo Posts: 306 Joined: Jun 12, 2008 Last seen: Jan 6, 2020
Are you running a simulation? Is your or1200 release 3? Are you running a simulation? Is your or1200 release 3?

RE: minsoc: Starting CPU error by rfajardo on Aug 12, 2010			rfajardo Posts: 306 Joined: Jun 12, 2008 Last seen: Jan 6, 2020
Yes, I have the same problem here. Edit start_server removing the -t option. It is some issue with the Advanced Debug System and or1200_r3. Yes, I have the same problem here. Edit start_server removing the -t option. It is some issue with the Advanced Debug System and or1200_r3.

RE: minsoc: Starting CPU error by julius on Aug 12, 2010			julius Posts: 363 Joined: Jul 1, 2008 Last seen: May 17, 2021
Yes, I need to change the default boot PC for the processor in the repository. At the moment it's 0xf0000100 (although EPH bit is still low). Although maybe that's not the issue. Yes, I need to change the default boot PC for the processor in the repository. At the moment it's 0xf0000100 (although EPH bit is still low). Although maybe that's not the issue.

RE: minsoc: Starting CPU error by jb007 on Aug 12, 2010			jb007 Posts: 29 Joined: May 3, 2009 Last seen: Jun 29, 2020
[q]Yes, I have the same problem here. Edit start_server removing the -t option. It is some issue with the Advanced Debug System and or1200_r3. [/q] After a very looooong wait... all's OK. I think it's about time I updated my Pentium 4 3GHz system! Thanks everyone for your help. Jim Yes, I have the same problem here. Edit start_server removing the -t option. It is some issue with the Advanced Debug System and or1200_r3. After a very looooong wait... all's OK. I think it's about time I updated my Pentium 4 3GHz system! Thanks everyone for your help. Jim

RE: minsoc: Starting CPU error by rfajardo on Aug 12, 2010			rfajardo Posts: 306 Joined: Jun 12, 2008 Last seen: Jan 6, 2020
Hi Jim, it seems not to be clear in the howto document. But if you are only interested in seeing the output of a firmware (what you would receive on the computer through serial cable), start_server and gdb are not required. When you initialize the simulation with ./run_bench ../../sw/uart/uart-nocache-twobyte-sizefirst.hex the firmware is loaded by the simulation itself and run. The output will appear after some time on the simulation terminal as if it was a serial terminal. Furthermore you can enable the waveforms generation for the design simulation by uncommenting `define VCD_OUTPUT on minsoc_bench_defines.v. The waveform will be stored as "minsoc_wave.vcd" on "minsoc/sim/results". You can visualize that waveform with gtkwave for example. The debugging the simulation part is really there, only for the case where you have to debug the firmware you are developing. With it you can stop the CPU execution and step through your firmware. It is not really intended for running the firmware and checking it out. Best regards, Raul Hi Jim, it seems not to be clear in the howto document. But if you are only interested in seeing the output of a firmware (what you would receive on the computer through serial cable), start_server and gdb are not required. When you initialize the simulation with ./run_bench ../../sw/uart/uart-nocache-twobyte-sizefirst.hex the firmware is loaded by the simulation itself and run. The output will appear after some time on the simulation terminal as if it was a serial terminal. Furthermore you can enable the waveforms generation for the design simulation by uncommenting `define VCD_OUTPUT on minsoc_bench_defines.v. The waveform will be stored as "minsoc_wave.vcd" on "minsoc/sim/results". You can visualize that waveform with gtkwave for example. The debugging the simulation part is really there, only for the case where you have to debug the firmware you are developing. With it you can stop the CPU execution and step through your firmware. It is not really intended for running the firmware and checking it out. Best regards, Raul

RE: minsoc: Starting CPU error by jb007 on Aug 13, 2010			jb007 Posts: 29 Joined: May 3, 2009 Last seen: Jun 29, 2020
Hi Raul. Thanks for that, I'll give it a try. I'm a newbie with all of this. Thanks again. Jim Hi Raul. Thanks for that, I'll give it a try. I'm a newbie with all of this. Thanks again. Jim

RE: minsoc: Starting CPU error by nyawn on Aug 18, 2010			nyawn Posts: 173 Joined: Dec 19, 2008 Last seen: May 31, 2023
Yes, there appears to be some incompatibility with the OR1200v3 and the self-test that the Advanced Debug System uses. Since the self-test hasn't changed any, there are two possibilities: 1. The self-test, which was written many years ago for jp2/OR1200v1, depends on some sort of non-spec behavior of the OR1200, which has been 'fixed' in OR1200v3. 2. The OR1200v3 is broken. I haven't taken the time to figure out which it is, and at this point I'm not sure I care to. I'll try again once the new OR1200 has stabilized. Warning: even if you disable the self-test, you'll still have problems with ADS and OR1200v3. When I've tried it, the system (repeatably) stops responding the third time I do a stepi. YMMV. Yes, there appears to be some incompatibility with the OR1200v3 and the self-test that the Advanced Debug System uses. Since the self-test hasn't changed any, there are two possibilities: 1. The self-test, which was written many years ago for jp2/OR1200v1, depends on some sort of non-spec behavior of the OR1200, which has been 'fixed' in OR1200v3. 2. The OR1200v3 is broken. I haven't taken the time to figure out which it is, and at this point I'm not sure I care to. I'll try again once the new OR1200 has stabilized. Warning: even if you disable the self-test, you'll still have problems with ADS and OR1200v3. When I've tried it, the system (repeatably) stops responding the third time I do a stepi. YMMV.

RE: minsoc: Starting CPU error by scutwengxinqian on Jan 7, 2013			scutwengxinqian Posts: 3 Joined: May 24, 2011 Last seen: Oct 11, 2014
I'm running into the same problem. openrisc@openrisc-VirtualBox:~$ adv_jtag_bridge -t ft245 'usb_blaster' interface using libftdi current latency timer: 2 Enumerating JTAG chain... Devices on JTAG chain: Index Name ID Code IR Length ---------------------------------------------------------------- 0: EP4CE115F29 0x020F70DD 10 Target device 0, JTAG ID = 0x020f70dd IDCODE sanity test passed, chain OK! * Doing self-test * Stall or1k - CPU(s) stalled. SRAM test: expected 11112222, read 11112222 expected 33334444, read 33334444 expected 55556666, read 55556666 expected 77778888, read 77778888 expected 9999aaaa, read 9999aaaa expected bbbbcccc, read bbbbcccc expected ddddeeee, read ddddeeee expected ffff0000, read ffff0000 expected dedababa, read dedababa SRAM test passed Testing CPU0 (or1k) - writing instructions Setting up CPU0 Starting CPU0! Read npc = 00000010 ppc = 00000028 r1 = 00000005 Expected npc = 00000010 ppc = 00000028 r1 = 00000005 Read npc = 00000028 ppc = 00000028 r1 = 00000008 Expected npc = 00000010 ppc = 00000028 r1 = 00000008 Read npc = 00000024 ppc = 00000020 r1 = 0000000b Expected npc = 00000028 ppc = 00000024 r1 = 0000000b Read npc = 00000020 ppc = 00000020 r1 = 00000018 Expected npc = 00000024 ppc = 00000020 r1 = 00000018 Read npc = 0000001c ppc = 00000018 r1 = 00000031 Expected npc = 00000020 ppc = 0000001c r1 = 00000031 Read npc = 00000020 ppc = 0000001c r1 = 00000032 Expected npc = 00000024 ppc = 00000020 r1 = 00000032 Read npc = 00000010 ppc = 00000028 r1 = 00000063 Expected npc = 00000014 ppc = 00000010 r1 = 00000063 Read npc = 00000024 ppc = 00000020 r1 = 00000065 Expected npc = 00000028 ppc = 00000024 r1 = 00000065 Read npc = 00000010 ppc = 00000028 r1 = 000000c9 Expected npc = 00000010 ppc = 00000028 r1 = 000000c9 result = deaddeb5 Self-test FAILED * Bailing out! I'm running into the same problem. openrisc@openrisc-VirtualBox:~$ adv_jtag_bridge -t ft245 'usb_blaster' interface using libftdi current latency timer: 2 Enumerating JTAG chain... Devices on JTAG chain: Index Name ID Code IR Length ---------------------------------------------------------------- 0: EP4CE115F29 0x020F70DD 10 Target device 0, JTAG ID = 0x020f70dd IDCODE sanity test passed, chain OK! * Doing self-test * Stall or1k - CPU(s) stalled. SRAM test: expected 11112222, read 11112222 expected 33334444, read 33334444 expected 55556666, read 55556666 expected 77778888, read 77778888 expected 9999aaaa, read 9999aaaa expected bbbbcccc, read bbbbcccc expected ddddeeee, read ddddeeee expected ffff0000, read ffff0000 expected dedababa, read dedababa SRAM test passed Testing CPU0 (or1k) - writing instructions Setting up CPU0 Starting CPU0! Read npc = 00000010 ppc = 00000028 r1 = 00000005 Expected npc = 00000010 ppc = 00000028 r1 = 00000005 Read npc = 00000028 ppc = 00000028 r1 = 00000008 Expected npc = 00000010 ppc = 00000028 r1 = 00000008 Read npc = 00000024 ppc = 00000020 r1 = 0000000b Expected npc = 00000028 ppc = 00000024 r1 = 0000000b Read npc = 00000020 ppc = 00000020 r1 = 00000018 Expected npc = 00000024 ppc = 00000020 r1 = 00000018 Read npc = 0000001c ppc = 00000018 r1 = 00000031 Expected npc = 00000020 ppc = 0000001c r1 = 00000031 Read npc = 00000020 ppc = 0000001c r1 = 00000032 Expected npc = 00000024 ppc = 00000020 r1 = 00000032 Read npc = 00000010 ppc = 00000028 r1 = 00000063 Expected npc = 00000014 ppc = 00000010 r1 = 00000063 Read npc = 00000024 ppc = 00000020 r1 = 00000065 Expected npc = 00000028 ppc = 00000024 r1 = 00000065 Read npc = 00000010 ppc = 00000028 r1 = 000000c9 Expected npc = 00000010 ppc = 00000028 r1 = 000000c9 result = deaddeb5 Self-test FAILED * Bailing out!

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