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DE2-70 + Orpsoc + Linux
by parrado on Nov 25, 2010
parrado
Posts: 19
Joined: Jul 16, 2008
Last seen: Nov 12, 2020
I want to implement an orpsoc Linux based system on my DE2-70 development board.

I have tested MINSOC (with onchip memory) satisfactorily.

Now I want to include a SDRAM memory controller in order to increase memory size and test Linux.

I'm supposing my system should include following cores in order to run Linux:

-- According to orsoc development board (one of Linux supported boards), versatile memory controller should be used.

-or1200 core with tick timer enabled.

--A UART.

For a minimal Linux based system, It is sufficient theese 3 cores.

Theese 4 guesses are true?


There are restrictions related to modules base addresses?

Does Linux kernel use fixed base addresses? In that case, which are their values?




What means "memory controller version 1 or 2" during Linux configuration? I am getting error when a 50 MHz clock is selected.

Can compiled Linux image be downloaded using adv_dbg + adv_jtag_bridge + GDB?


Thanks in advance.

Best regards,


Alex Parrado.
RE: DE2-70 + Orpsoc + Linux
by julius on Nov 25, 2010
julius
Posts: 363
Joined: Jul 1, 2008
Last seen: May 17, 2021
Now I want to include a SDRAM memory controller in order to increase memory size and test Linux.

I'm supposing my system should include following cores in order to run Linux:

-- According to orsoc development board (one of Linux supported boards), versatile memory controller should be used.

Any appropriate memory controller will do. You're not required to use the versatile memory controller. I'm not sure what the minimum size RAM you need to run the kernel, and do something useful with it, but probably at least 16 to 32MB.

-or1200 core with tick timer enabled.

You need more than that. You need instruction and data MMUs too, and I would strongly recommend using at least instruction cache, and both instruction and data caches if you can fit it on the FPGA.

--A UART.

Most definitely.

There are restrictions related to modules base addresses?

That's a good question. The original ORPSoC had with it an ORP address space mapping. It looks like this:
OpenRISC Reference Platform (ORP)

Address Space

0xf000_0000 - 0xffff_ffff Cached 256MB ROM
0xc000_0000 - 0xefff_ffff Cached 768MB Reserved
0xb800_0000 - 0xbfff_ffff Uncached 128MB Reserved for custom devices
0xa600_0000 - 0xb7ff_ffff Uncached 288MB Reserved
0xa500_0000 - 0xa5ff_ffff Uncached 16MB Debug 0-15
0xa400_0000 - 0xa4ff_ffff Uncached 16MB Digital Camera Controller 0-15
0xa300_0000 - 0xa3ff_ffff Uncached 16MB I2C Controller 0-15
0xa200_0000 - 0xa2ff_ffff Uncached 16MB TDM Controller 0-15
0xa100_0000 - 0xa1ff_ffff Uncached 16MB HDLC Controller 0-15
0xa000_0000 - 0xa0ff_ffff Uncached 16MB Real-Time Clock 0-15
0x9f00_0000 - 0x9fff_ffff Uncached 16MB Firewire Controller 0-15
0x9e00_0000 - 0x9eff_ffff Uncached 16MB IDE Controller 0-15
0x9d00_0000 - 0x9dff_ffff Uncached 16MB Audio Controller 0-15
0x9c00_0000 - 0x9cff_ffff Uncached 16MB USB Host Controller 0-15
0x9b00_0000 - 0x9bff_ffff Uncached 16MB USB Func Controller 0-15
0x9a00_0000 - 0x9aff_ffff Uncached 16MB General-Purpose DMA 0-15
0x9900_0000 - 0x99ff_ffff Uncached 16MB PCI Controller 0-15
0x9800_0000 - 0x98ff_ffff Uncached 16MB IrDA Controller 0-15
0x9700_0000 - 0x97ff_ffff Uncached 16MB Graphics Controller 0-15
0x9600_0000 - 0x96ff_ffff Uncached 16MB PWM/Timer/Counter Controller 0-15
0x9500_0000 - 0x95ff_ffff Uncached 16MB Traffic COP 0-15
0x9400_0000 - 0x94ff_ffff Uncached 16MB PS/2 Controller 0-15
0x9300_0000 - 0x93ff_ffff Uncached 16MB Memory Controller 0-15
0x9200_0000 - 0x92ff_ffff Uncached 16MB Ethernet Controller 0-15
0x9100_0000 - 0x91ff_ffff Uncached 16MB General-Purpose I/O 0-15
0x9000_0000 - 0x90ff_ffff Uncached 16MB UART16550 Controller 0-15
0x8000_0000 - 0x8fff_ffff Uncached 256MB PCI I/O
0x4000_0000 - 0x7fff_ffff Uncached 1GB Reserved
0x0000_0000 - 0x3fff_ffff Cached 1GB RAM

Interrupts

0 Reserved
1 Reserved
2 UART16550 Controller 0
3 General-Purpose I/O 0
4 Ethernet Controller 0
5 PS/2 Controller 0
6 Traffic COP 0, Real-Time Clock 0
7 PWM/Timer/Counter Controller 0
8 Graphics Controller 0
9 IrDA Controller 0
10 PCI Controller 0
11 General-Purpose DMA 0
12 USB Func Controller 0
13 USB Host Controller 0
14 Audio Controller 0
15 IDE Controller 0
16 Firewire Controller 0
17 HDLC Controller 0
18 TDM Controller 0
19 I2C Controller 0, Digital Camera Controller 0


I'm not sure how much we want to adhere to this, or if we should define a new one. I'm happy for this to be up for discussion.

Does Linux kernel use fixed base addresses? In that case, which are their values?

The most recent OpenRISC Linux port (which we should update the information on shortly) contains configurable peripheral addresses using device tree blobs and associated configuration files. The new ORPSoC board builds can run Linux according to this configuration.


What means "memory controller version 1 or 2" during Linux configuration? I am getting error when a 50 MHz clock is selected.

This is from the older Linux build - the new one doesn't need this configuration as we no longer use a memory controller requiring initialisation with parameters.

Can compiled Linux image be downloaded using adv_dbg + adv_jtag_bridge + GDB?

Yes.
RE: DE2-70 + Orpsoc + Linux
by parrado on Nov 25, 2010
parrado
Posts: 19
Joined: Jul 16, 2008
Last seen: Nov 12, 2020
Thanks a lot for your reply.

You need more than that. You need instruction and data MMUs too, and I would strongly recommend using at least instruction cache, and both instruction and data caches if you can fit it on the FPGA.


Ok, I had them.



That's a good question. The original ORPSoC had with it an ORP address space mapping. It looks like this:
OpenRISC Reference Platform (ORP)


Does the kernel assume a Static RAM space?


The most recent OpenRISC Linux port (which we should update the information on shortly) contains configurable peripheral addresses using device tree blobs and associated configuration files. The new ORPSoC board builds can run Linux according to this configuration.


Great!!




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