Hi all;

is it correct way to convert std_logic_vector to unsigned integer?

signal statereg : std_logic_vector(31 downto 0);

signal statereg := std_logic_vector(to_unsigned(int,statereg'length));

Thanks in advance.

Regards
Raghavendra

yes

Thanks..

Regards
Raghavendra

Hi Olof,

To convert std_logic_vector to integer i used below statment

signal statereg := std_logic_vector(to_unsigned(int,statereg'length));

in ghdl simulator after compilation error.

error:no declaration for "int"

Thanks in advance

Regards
Raghavendra

Hi,

Use the following steps,

1. Include the Arith library

LIBRARY IEEE;
USE IEEE.STD_LOGIC_ARITH.ALL;

2. To convert from Integer to STD_LOGIC_VECTOR, use

SIGNAL s:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL i:INTEGER;

s
3. To convert from STD_LOGIC_VECTOR to Integer, use

i

You shouldn't use std_logic_arith. Use ieee.numeric_std instead. It's the official IEEE standard library. std_logic_arith was something synopsys invented, and should have been deprecated by now

As for the undefined int problem.. are you sure that you have declared a variable or signal that is called int? It looks like it can't find the int object

Thanks for your replies ..

you should use library arith and unsigned and 1164 of ieee
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
.
.
.
var_a:=conv_integer(var_b,var_a'length);
.
.
.

You still shouldn't be using std_arith. numeric_std is the standardized package and contains both signed and unsigned types and convertion functions

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

signal i : integer;
signal s : std_logic_vector(7 downto 0);

s <= std_logic_vector(to_unsigned(i,s'length));

--
Olof Kindgren
______________________________________________
ORSoC
Website: www.orsoc.se
Email: olof.kindgren@orsoc.se
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FPGA, ASIC, DSP - embedded SoC design