OpenCores
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usb2 core / PHY ISP1501
by Unknown on Feb 26, 2004
Not available!
hello everybody,

for our (my colleague and i) graduation project we need to implement a
usb 2 (device) link in a prototyping system. This system consists of a
philips ISP1501-01 IC and an FPGA. We intended to use the usb 2 core
by rudi in the fpga, since the documentation stated it supported the
1501.

However, the 1501 does not seem to comply with the core's UMTI
interface type. The core uses a double (tx/rx) 8 bit wide interface @ 60
MHz, whereas the 1501 can only be used with the 16 bit wide
(bidirectional) interface @ 30 MHz. BTW i hope somebody can prove me
wrong here... :-)

Hence i would like to know if somebody has a workaround for this
problem, or do we need to rewrite the entire core for a 16 bit wide bus?
Has anybody actually used the 2.0 core succesfully for that matter?

We are not native verilog developers ( we were tought VHDL) though it
should probably not be a problem to learn that language...

If nobody has used this core in conjunction with the 1501 we would
maybe like to contribute by either writing a workaround or modifying the
core so that it can work with both 8bit 60 MHz or 16 bit 60 MHz (only if
that option proves to be not too much of a hastle).

Regards,

Egwin Wesselink
usb2 core / PHY ISP1501
by Unknown on Mar 4, 2004
Not available!
----- Original Message ----- From: wesselin@n...wesselin@n...> To: Date: Thu Feb 26 13:07:12 CET 2004 Subject: [usb] usb2 core / PHY ISP1501
hello everybody,

for our (my colleague and i) graduation project we need to
implement a
usb 2 (device) link in a prototyping system. This system consists
of a
philips ISP1501-01 IC and an FPGA. We intended to use the usb 2
core
by rudi in the fpga, since the documentation stated it supported
the
1501.
However, the 1501 does not seem to comply with the core's UMTI
interface type. The core uses a double (tx/rx) 8 bit wide interface
@ 60
MHz, whereas the 1501 can only be used with the 16 bit wide
(bidirectional) interface @ 30 MHz. BTW i hope somebody can prove
me
wrong here... :-)
Hence i would like to know if somebody has a workaround for this
problem, or do we need to rewrite the entire core for a 16 bit wide
bus?
Has anybody actually used the 2.0 core succesfully for that matter?
We are not native verilog developers ( we were tought VHDL) though
it
should probably not be a problem to learn that language...
If nobody has used this core in conjunction with the 1501 we would
maybe like to contribute by either writing a workaround or
modifying the
core so that it can work with both 8bit 60 MHz or 16 bit 60 MHz
(only if
that option proves to be not too much of a hastle).
Regards,
Egwin Wesselink



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