OpenCores
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AVALON / WISHBONE bridge
by Unknown on Nov 8, 2006
Not available!
I am in the search of an interface between a bus AVALON and WISHBONE
with and without DMA.
Somebody with already developed something partially or entirely ?


Wishbone is almost a subset of Avalon. Avalon comes in many different
versions and one can be (more or less) directly mapped to Wishbone.
See the Avalon specification. Should be possible with a few clicks
in the SOPC builder.

Martin


AVALON / WISHBONE bridge
by Unknown on Nov 8, 2006
Not available!
Hello,
I am in the search of an interface between a bus AVALON and WISHBONE
with and without DMA.
Somebody with already developed something partially or entirely ?

AVALON / WISHBONE bridge
by Unknown on Nov 9, 2006
Not available!
I noted. To make transfer not DMA, it there not true problem. But my big problem is to make transfer in more DMA. AVALON hopes the number of byte to be transferred and WISHBONE make bagotté of the logical signals. Before launched me in development, I wanted to know if somebody it is already leaning on the feasibility of interphase between the two operating modes of the buses. Thank you by advance to agree to answer. ----- Original Message ----- From: Martin Schoeberlmartin at j...> To: Date: Wed Nov 8 18:45:25 CET 2006 Subject: [oc] AVALON / WISHBONE bridge
> I am in the search of an interface between a bus AVALON and

WISHBONE
> with and without DMA.
> Somebody with already developed something partially or

entirely ?
Wishbone is almost a subset of Avalon. Avalon comes in many
different
versions and one can be (more or less) directly mapped to Wishbone.
See the Avalon specification. Should be possible with a few clicks
in the SOPC builder.
Martin




AVALON / WISHBONE bridge
by Unknown on Mar 6, 2007
Not available!
I'm looking for a avalon/wishbone bridge, in order to use it in sopc builder, someone could help me? ----- Original Message ----- From: michael.sevrain at voila.frmichael.sevrain at v...> To: Date: Wed Nov 8 20:45:44 CET 2006 Subject: [oc] AVALON / WISHBONE bridge
Hello,
I am in the search of an interface between a bus AVALON and
WISHBONE
with and without DMA.
Somebody with already developed something partially or entirely ?




AVALON / WISHBONE bridge
by Unknown on Mar 6, 2007
Not available!
michael.sevrain at voila.fr wrote:
I noted. To make transfer not DMA, it there not true problem. But my
big problem is to make transfer in more DMA. AVALON hopes the number
of byte to be transferred and WISHBONE make bagotté of the logical
signals. Before launched me in development, I wanted to know if
somebody it is already leaning on the feasibility of interphase
between the two operating modes of the buses. Thank you by advance to
agree to answer.
There is no issue with Avalon/Wishbone DMA. I've successfully used the SOPC DMA controller with the opencores (wishbone) IDE controller. Everything is done within SOPC builder - no extra logic required. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266
AVALON / WISHBONE bridge
by Unknown on Mar 6, 2007
Not available!
visman.pulendran at isep.fr wrote:
I'm looking for a avalon/wishbone bridge, in order to use it in sopc
builder, someone could help me?
There is no bridge - it is not required. Create a 'component' within SOPC for your wishbone IP. The signals mappings are quite obvious, except perhaps ACK==waitrequest_n. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266
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