The built-in DLC9 is not a real JTAG cable. You need to have GENERIC_TAP commented and uncomment FPGA_TAP and XILINX_FPGA.

Thanks firefalcon.

The cable I have is not the DCL9, mine is DCL9G what is from computer usb to a blackbox and from blackbox JTAG (tdi,tdo,tck,etc.)to FPGA board.

Then I uncomment define GENERIC_JTAG and define XILINX_FPGA, comment define FPGA_TAP.

is it right?

If you were using a stand-alone JTAG cable (DLC9 or any other), and attaching it to a JTAG port you created using the GPIO pins of the FPGA, then using GENERIC_JTAG would be correct.

However, based on the JTAG chain enumeration output by adv_jtag_bridge, that's not what you're doing. Your JTAG chain has 3 Xilinx devices on it including your FPGA, meaning that you are attaching your JTAG cable to the dedicated JTAG port of the FPGA, the same port you use to download the bitstream to the FPGA. In this case, you need to use FPGA_TAP and XLINIX_FPGA.

If you want to know more about why, I suggest you read the top-level documentation for the adv. debug system, it gives an overview of the various TAP modules and when they're used.