Today, deep submicron (DSM) designs include many millions of gates in a single application-specific integrated circuit (ASIC). The number of gates continues to grow, with the result that design times get longer and longer. This can result in excessive time- to-market and excessive cost.
The technical solution to the problem is to reuse cores and to shared the expending workload of verification.
Currently, cores available for integration are proprietary and must be purchased from established vendors, often at very high prices. These costs can be burdensome, especially for small design teams with limited funding. Proprietary cores are hard to integrate due to the multiplicity of incompatible design and test tools.
Our main objective is to design and publish core designs under a license for hardware modeled on the Lesser General Public License (LGPL) for software. We are committed to the ideal of freely available, freely usable and re-usable open source hardware.
We have set the following objectives as the means of reaching our main objective:
- Develop standards for open source cores and platforms
- Create tools and methods for development of open source cores and platforms
- Develop open source cores and platforms
- Provide documentation for these cores and platforms
Open source hardware is the solution to most of the problems associated with proprietary cores. It has the following benefits.
- Each core will have a larger user base, which will ensure better support, better documentation and better implementation examples to work from.
- The source is available, so any developer can find out what he or she needs to know about the core.
- There is no charge for using the core.
- Eventually, as cores and standards for them are developed, cores will become more standards-compliant than proprietary cores.
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