OpenCores

OPENCORES: Tools

Introduction

OpenCores is the world largest community focusing on open source development targeted for hardware. Designing IP cores, is unfortunately not as simple as writing a C program. A lot more steps are needed to verify the cores and to ensure they can be synthesized to different FPGA architectures and various standard cell libraries.

Open Source EDA tools

There are plenty of good EDA tools that are open source available. The use of such tools makes it easier to collaborate at the opencores site. An IP that has readily available scripts for an open source HDL simulator makes it easier for an other person to verify and possibly update that particular core. A test environment that is built for a commercial simulator that only a limited number of people have access to makes verification more complicated.

Icarus Verilog Simulator

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the &qout;vvp&qout; command. For synthesis, the compiler generates netlists in the desired format.

The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2005.

Icarus web site

Verilator

Verilator is a free Verilog HDL simulator. It compiles synthesizable Verilog into an executable format and wraps it into a SystemC model. Internally a two-stage model is used. The resulting model executes about 10 times faster than standalone SystemC.

Verilator has been used to simulate many very large multi-million gate designs with thousands of modules. Therefor we have chosen this tool to be used in the verification environment for the OpenRISC processor.

Verilator web site

GHDL VHDL simulator

GHDL implements the VHDL87 (common name for IEEE 1076-1987) standard, the VHDL93 standard (aka IEEE 1076-1993) and the protected types of VHDL00 (aka IEEE 1076a or IEEE 1076-2000). The VHDL version can be selected with a command line option.

GHDL web site

EMACS - text editor

GNU Emacs is an extensible, customizable text editor—and more.

Very good support for both Verilog HDL and VHDL editing.

Emacs web site

Fizzim is a FREE, open-source GUI-based FSM design tool

The GUI is written in java for portability. The backend code generation is written in perl for portability and ease of modification.

Features:

GUI:

  • Runs on Windows, Linux, Apple, anything with java.
  • Familiar Windows look-and-feel.
  • Visibility (on/off/only-non-default) and color control on data and comment fields.
  • Multiple pages for complex state machines.
  • "Output to clipboard" makes it easy to pull the state diagram into your documentation.

Backend:

  • Verilog code generation based on recommendations from experts in the field.
  • Output code has "hand-coded" look-and-feel (no tasks, functions, etc).
  • Switch between highly encoded or onehot output without changing the source.
  • Registered outputs can be specified to be included as state bits, or pulled out as independent flops.
  • Mealy and Moore outputs available.
  • Transition priority available.
  • Automatic grey coding available.
  • Code and/or comments can be inserted at strategic places in the output - no need to "perl" the output to add your copyright or `include

Fizzim web site

TCE

TCE is a toolset for designing application-specific processors (ASP) based on the Transport triggered architecture (TTA). The toolset provides a complete co-design flow from C programs down to synthesizable VHDL and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network.

TCE has been developed internally in the Tampere University of Technology since the early 2003. The current source code base consists of roughly 400 000 lines of C++ code.

TCE web site

C to Verilog translation

Available is an online C to Verilog compiler. The code generated by the site is licensed under BSD (use it "as is").

C-to-Verilog web site

Fedora Electronic Lab

Fedora Electronic Lab tries to provide a complete hardware design flow with the best opensource tools. We try to ensure interoperability as far as we can and we work with other opensource developers to improve existing EDA tools.

Fedora Electronic Lab web site

Contact

For more information please contact:

OpenCores Administration:

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