3DES (Triple DES) / DES (VHDL) :: Overview
Other project properties
This is a VHDL implementation of Triple-DES (pipelined) and DES cryptographic algorithms, as recommended by NIST.
In our tests the core has been verified to comply with the http://csrc.nist.gov/publications/fips/fips46-3/fips46-3.pdf (NIST FIPS 46-3) (DES)recommendation.
This core is provided by:
http://www.coretexsys.com (Coretex Systems, LLC)
- Pipelined architecture.
- VHDL source code.
- Verified in hardware.
- Small footprint (the numbers are for Xilinx Virtex 2 FPGA)
- 1742 slices,
- 302 IOBs,
- no block RAMs,
- 1 GCLK.
- Fast processing (the numbers assume the pipeline is fully utilized)
- An output each 17 clocks.
- Maximum operating frequency 162 MHz.
- Bandwidth ~581 Mb/s.