OpenCores

8b10b Encoder/Decoder :: Overview

Project maintainers

Details

Name: 8b10b_encdec
Created: Sep 11, 2006
Updated: May 9, 2013
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Communication controller
Language: VHDL
Development status: Stable
Additional info: Design done
WishBone Compliant: No
License: GPL

Description

This project, written in generic synthesizable VHDL, provides two separate cores for encoding and decoding byte data according to the 8b/10b protocol. 8b/10b is widely used in high speed serial communication standards that need a run-length limited, DC balanced data stream for reliable data transmission and clock recovery. The encoder accepts a parallel 8-bit raw input and generates a parallel 10-bit encoded value based on the data along with a running disparity value. The decoder does the reverse, providing a decoded 8-bit value from the 10-bit encoded input. These cores can be easily incorporated into serializer/deserializer (serdes) communications applications.

Features:

The two main modules provide a complete VHDL implementation that closely follows the original IBM article "A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code" published by A.X. Widmer and P.A. Franaszek and the resulting US patent #4,486,739. For clarity, the VHDL code references the figures and tables of the patent document. Please note that the patent has now expired.

Encoder:
+ 8b/10b Encoder (file: 8b10b_enc.vhd)
+ Synchronous clocked inputs (latched on each clock rising edge)
+ 8-bit parallel unencoded data input
+ KI input selects data or control encoding
+ Asynchronous active high reset initializes all logic
+ Encoded data output
+ 10-bit parallel encoded output valid 1 clock later

Decoder:
+ 8b/10b Decoder (file: 8b10b_dec.vhd)
+ Synchronous clocked inputs (latched on each clock rising edge)
+ 10-bit parallel encoded data input
+ Asynchronous active high reset initializes all logic
+ Decoded data, disparity and KO outputs
+ 8-bit parallel unencoded output valid 1 clock later

There are two Testbench files; one that tests the encoder and a second that drives the decoder with the latched output from the encoder. All 256 data characters, "D", and all 12 control characters , "K", are sequenced.

- Encoder Testbench (file: enc_8b10b_TB.vhd)

- Combined Testbench (file: endec_8b10b_TB.vhd)

Status

The two source files and the two testbench files are now complete and have been functionally simulated. The files, and a brief usage document have been uploaded to CVS

© copyright 1999-2014 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.