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adat receiver :: Overview

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Details

Name: adat_optical_feed_forward_receiver
Created: Jul 25, 2008
Updated: Dec 20, 2009
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Communication controller
Language: VHDL
Development status: Stable
Additional info: FPGA proven
WishBone compliant: No
WishBone version: n/a
License:

Description

This is a feed forward receiver for an ADAT lightpipe optical datastream. This type of multichannel audio connection is widely used in professional digital recording studios. It consists of eight 24 bit wide audio words, at a sample rate (wordclock) of 32kHz, 44,1kHz or 48kHz. It can double the sample rate at the cost of half the number of channels, this is called S-MUX (not supported yet). There are 4 user bits to carry extra data (MIDI, S-MUX indicator, timecode and spare). ADAT streams are encoded with NRZI coding, meaning a change in the ADAT stream is a "1", with no change a "0" is sent.

The receiver needs one extra input besides the ADAT stream: Any stable clock (m_clk) between 80MHz and 160MHz should work.

One instance is used: a 12x8 multiplier with the 12 MSB's output. Compiled for an Altera Cyclone II the design uses 682LE's and 2 embedded 9 bit multipliers.

I'm glad to announce that I finally had the opportunity to test and optimize this design, and it's now FPGA proven. I also slimmed down the design to 682LE's. If you are using this design in a larger project, and have no use for a bus-like interface, the registers can be implemented in M4K blocks in the Altera Cyclone II, and it uses even less LE's (I think in the 250-300 range).

Features

- feed forward: other than a non-related clock signal, only the ADAT data stream is required.
- outputs the 8 audio words on a databus.
- regenerates the wordclock from the received stream.
- outputs the user bits as seperate pins.
- adapts to speed changes.
- should (!) lock on to the stream in a matter of seconds.

Status

- VHDL code written
- testbench completed
- simulation of design
- Tried the design in an FPGA.

Todo:
- comment the code.

IMAGE: thumb_waves1.jpg

FILE: thumb_waves1.jpg
DESCRIPTION: Some ADAT frames in simulation

IMAGE: thumb_waves2.jpg

FILE: thumb_waves2.jpg
DESCRIPTION: Frame delimiter closeup

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