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ae18 :: Overview

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Details

Name: ae18
Created: Aug 7, 2003
Updated: Dec 20, 2009
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Processor
Language: Verilog
Development status: Beta
Additional info: Design done
WishBone compliant: Yes
WishBone version: n/a
License: LGPL

Description

The AE18 is a clean room implementation of the Microchip PIC18 series CPU core using information from the PIC18C documentation from their website. It is cycle and instruction compatible to the PIC18 for most software commands. This is just a CPU core that is capable of moving and manipulating data to and from memory. It does not have any peripherals nor interrupt controllers although support for both high and low level interrupts are provided. Any peripherals and their respective registers should be mapped to the data memory space. It has a separate instruction and data bus.

Features

- Harvard architecture with separate instruction and data bus.
- Wishbone compatible bus.
- Full 24bits instruction memory capable.
- Full 16bits data memory capable.
- Custom user peripheral/interrupt controllers.

Status

- Tested in software simulation running C code compiled using SDCC 2.5 and GPUTILS 0.13.4.
- Simulated using both Icarus Verilog 0.8.2 and GPLCVER 2.11a.
- Simulation results verified against GPSIM 0.22.0.
- Synthesised for 25k gates @ 50 MHz on a Spartan3 with ISE.
- This initial revision of the design can definitely be further optimised.
- Drop me an email to inform me if you use this core in any of your projects.

Notes

Please test it extensively before using. Although every care has been taken to test this core, it is supplied WITHOUT WARRANTY of any kind. If you do find bugs, please feel free to report it using the bug tracker. In order to facilitate debugging, please include any code sequence that is necessary to reproduce the bug. Also, any other information that is necessary will be greatly appreciated.

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