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aeMB :: Overview

Project maintainers

Details

Name: aemb
Created: Aug 10, 2004
Updated: Dec 20, 2009
SVN Updated: Jul 25, 2009
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Processor
Language: Verilog
Development status: Beta
Additional info: Design done, FPGA proven
WishBone Compliant: Yes
License: LGPL

Features

- Non-architecture compatible with MB.
- Harvard architecture with separate instruction and data bus.
- Provides GET/PUT implementation on a FSL bus.
- Uses WISHBONE instead of LMB/OPB bus protocol for I/O.
- Fully pipelined for single cycle execution of all instructions.
- Single cycle barrel shifter and multiplier.
- Instruction compatible except for optional instructions not used in GCC.
- Missing: WIC,WDC,IDIV,IDIVU
- Optional parameterised multiplier and barrel shifter.
- Software division
- Software floating-point

Status

- Tested in software simulation:
- Simulated using both Icarus Verilog 0.8.5 and GPLCVER 2.11a.
- C code compiled with GCC 3.4.1 ( Xilinx EDK 8.1.01 Build EDK_I.19.4 061107).
- Fibonacci numbers (integer)
- Euclidean algorithm (modulo)
- Newton-Rhapson method (floating point)
- Some ISE synthesis results:
- 38k gates @ 88 MHz on Virtex4 (with hardware multiplier and barrel shifter).
- 38k gates @ 136 MHz on Virtex4 (with barrel shifter).
- Tested and independently proven in FPGA hardware.
- Drop me an email to inform me if you use this core in any of your projects.

Description

The aeMB is a clean room implementation of the EDK3.2 compatible Microblaze core using information from the Internet. It is cycle and instruction compatible to the MB for most software commands. It is not meant as a drop in replacement for the Microblaze as it is not 100% architecturally compatible. This is a CPU core that is capable of moving and manipulating data to and from memory. It does not have any peripherals nor interrupt controllers although support for external interrupts is provided. Any peripherals and their respective registers could be mapped to the data memory or FSL memory space. It has a separate instruction, data and FSL buses.

Notes

Please test it extensively before using. Although every care has been taken to test this core, it is supplied WITHOUT WARRANTY of any kind. If you do find bugs, please feel free to report it using the bug tracker. In order to facilitate debugging, please include any code sequence that is necessary to reproduce the bug. Also, any other information that is necessary will be greatly appreciated.

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