AltOr32 - Alternative Lightweight OpenRisc CPU :: Overview
Project maintainers
Details
Name: altor32
Created: Jun 9, 2012
Updated: Jul 7, 2012
SVN Updated: Mar 10, 2013
SVN: Browse
Latest version: download
Statistics: View
Other project properties
Category: Processor
Language: Verilog
Development status: Beta
Additional info:
FPGA proven
WishBone Compliant: No
License: LGPL
Description
AltOR32 is an OpenRISC 1000 architecture derived RISC CPU targeted at small FPGAs and contains only the most basic ISA features from the OpenRisc project.
Instructions & registers relating to Vector, floating-point, 64-bit extensions, MMU & Cache have been omitted.
The aim of AltOR32 is to provide a simple 32-bit soft CPU architecture aimed at control applications that can fit in low-end FPGA technology.
This architecture re-uses the OpenRisc GNU toolchain hence implements all instructions that cannot be disabled. Anything else is viewed as beyond the scope of this cut-down soft-CPU implementation.
Current Status
- Instruction set simulator created & functional
- Two core versions, one multi-cycle and the other pipelined.
- Basic implementation with UART & Timer fits in XC3S250E (around 59% of slices used).
- Toolchain: ftp://ocuser:ocuser@openrisc.opencores.org/toolchain/or32-elf-1.0rc1-x86.tar.bz2
Simulator
- A simple simulator for OpenRisc instructions, where only the essentials have been implemented.
- Compiles under Linux (GCC) or Windows (VS2003+).
- Able to execute OpenRisc 1000 (ORBIS32) code compiled with the following options:
-msoft-div -msoft-float -msoft-mul -mno-ror -mno-cmov -mno-sext
- Extensible