Reduced AVR Core for CPLD :: Overview

Project maintainers


Name: avr8
Created: Jul 30, 2010
Updated: Aug 29, 2010
SVN Updated: Jul 30, 2010
SVN: Browse
Latest version: download
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Other project properties

Category: Processor
Language: Verilog
Development status: Beta
Additional info: none
WishBone Compliant: No
License: LGPL


This CPU project does not implement fully AVR compatible core.
Instead it realizes very minimal functionality.
Task was to make kind of CPU that can fit into very small CPLD (Altera's EPM240T100C5) and still leave some space for other logic.
Development platform was choosed opensource "Marsohod" board. About this board You can read more on but it is Russian idea and pages. This board is dedicated for education, hobbies, creating electronic toys etc.

Board has 4 buttons, 8 LEDs, 2 step motor control sockets.

In AVR8 project we had implemented:
1) only four general purpose registers r16..r19;
2) general purpose register r20, bits connected to 8 LEDs of board
3) general purpose register r21, bits connected to 6 step motor output pins
4) read only register r22, low 4 bits read status of 4 board buttons.

Thus, no i/o ports, no timers, interrupts and other AVR features.
Anyway somehow this core is partly compatible to real microcontroller.
Altera's CPLD has User Flash Memory, so called UFM. It is organased as 512 words 16 bits each.
So AVR program can be stored there.

Project implements following AVR instructions:
ADD 0000 11rd dddd rrrr
SUB 0001 10rd dddd rrrr

AND 0010 00rd dddd rrrr
EOR 0010 01rd dddd rrrr
OR 0010 10rd dddd rrrr
MOV 0010 11rd dddd rrrr

CP 0001 01rd dddd rrrr
LSR 1001 010d dddd 0110

SUBI 0101 KKKK dddd KKKK
ANDI 0111 KKKK dddd KKKK
ORI 0110 KKKK dddd KKKK
CPI 0011 KKKK dddd KKKK
LDI 1110 KKKK dddd KKKK

BREQ 1111 00kk kkkk k001
BRNE 1111 01kk kkkk k001
BRCS 1111 00kk kkkk k000
BRCC 1111 01kk kkkk k000
Letter "d" encodes destination register.
Letter "r" encodes source register.
"k" encodes immediate values.

Core also inmpelemnts only two flags "Z" and "C".
Corresponding conditional jumps BREQ, BRNE, BRCS, BRCC were realized.
No real jumps of subrotine calls, no memory.

As resources are extremelly limited,
seems this cannot work, but test program was written in ATMEL AVRStudio.
Test application polls board buttons and blinks board LEDs accordingly.

Test application is that:

.include ""
.device AT90S1200

.org 0


;initial one bit in register
ldi r16,$80


;read port (key status)
mov r17,r22
cpi r17,$0f
;go and blink one LED if no key pressed
breq do_xor

cpi r17,$0e
;go and right shift LEDs if key[0] pressed
breq do_rshift

cpi r17,$0d
;go and left shift LEDs if key[1] pressed
breq do_lshift

;jump to read keys
or r16,r16
brne rd_port

cpi r16,1
breq set80
lsr r16
mov r20,r16
brne pause
ldi r16,$80
mov r20,r16
or r16,r16
brne pause

cpi r16,$80
breq set1
lsl r16
mov r20,r16
brne pause
ldi r16,$01
mov r20,r16
or r16,r16
brne pause

eor r20,r16

ldi r18,$10
ldi r19,$FF
or r19,r19
or r19,r19
subi r19,1
brne cycle1
subi r18,1
brne cycle2

or r16,r16
brne rd_port

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