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Connect-6 Solver :: Overview

Project maintainers

Details

Name: connect-6
Created: Oct 17, 2011
Updated: Feb 14, 2012
SVN Updated: May 17, 2012
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Other
Language: C/C++
Development status: Beta
Additional info: FPGA proven
WishBone compliant: No
WishBone version: n/a
License: GPL

CONNECT-6 SOLVER

Connect-6 is usually played on a 19 × 19 GO Board, with each player having either black or
white pieces. The Black starts the game with only one move, and after that each player makes
two moves at a time. The game stops when one of the player forms a vertical, horizontal or
diagonal line connecting six pieces of his color, or the board is full.


The fact that makes this game more interesting, is that each player makes two moves at a time,
except for the first move. This considerably increases the search space for moves and end-games.
Because of these reasons, Connect-6 has gained popularity in the AI community, and has been included
in the Computer Olympiad.

In this project we synthesize an open source connect-6 program( available at http://risujin.org/connectk/)
into hardware using HLS tools.

README

README:
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DEMO:

Before you begin exploring the project you can find demo files in the DEMO folder, which contains the original connect-k player, the bitstream for DE2 Board from ALTERA.

Download DE2.sof into the altera DE2 board, and connect it to your PC with RS232 cable.

Launch connectk and choose "serial port " in the drop down menu for players.

it should be able to play with the DE2 board now.
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BUILD_SCC:

In this folder you can run the complete build flow for synphonycc.

Install SYNPHONYCC, and QUARTUS, change the MaKefile so that the variable SCC point to your installation.
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Make Targets:

make: This will compile the golden "C" code (synthesizable) and run a test.

make synth: This will run the SCC flow, and generate RTL(verilog) which can be found in the folder rtl_package.

make altera_synth: This will generate the bitstream for DE2 board "DE2.sof". it depends on the previous target.

make fpga: This runs the complete flow downto testing the board.
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folders:

BUILD_SRC/synth_src: contains the synthesizable "C/C++" code, which is a modified version of original source code found in
CONNECTK folder.

BUILD_SRC/scc_scripts: contains the scripts for scc, whic are used when you do make synth.

DE2: Contains the wrapper code, pin assignments etc. for the DE2 board.
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