8080 Compatible CPU :: Overview

Project maintainers


Name: cpu8080
Created: Oct 4, 2006
Updated: Apr 28, 2016
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Processor
Language: Verilog
Development status: Stable
Additional info: Design done
WishBone Compliant: No


This is an 8080 core I created as a project to get to know Verilog.

The 8080 was the second in the series 8008->8080->Z80. It was the second
commercially available single chip CPU (disregarding the required
clock and multiplexer chips), after the 4 bit 4004. Besides being an interesting
project, it also can serve as a very compact core, suitable for a supervisor role on an
FPGA with other blocks. It has extensive support, all freely available, including
assemblers, compilers, an operating system (CP/M).

Although the Z80 is a more popular core due to being a superset of the 8080, the Z80
takes considerably more chip real estate. Its likely that more than 50% of available
software is 8080 only, since the Z80 was often used to run 8080 code. For example,
the CP/M OS itself was 8080 only code.

This means that the 8080 can be an attractive core if you want the great support of
this processor series, but need it to fit in less space.

The core is fully instruction compatible with 8080, but not signal compatible. The
original 8080 was a multiplexed nightmare. one of the original selling points of the Z80
was its cleanup of the signals, and the 8080 itself had a companion chip that
demultiplexed it.

There are a few other similar chips on opencores. This one is a bit different because
it is only 8080, and is in native Verilog (not a translation). Further, the goal was to
get it down to the minimum in both source size and synthesized size.

I also suspect there is a perverse advantage to running this core: its original
manufacturer no longer makes it, or any compatible chip, and it has probally passed
from any IP protection long ago. However, as usual, Should warn that I have not
verified any legal status on this processor and do not speak from any knowledge or
authority on the matter.


I did this core back in 2006. I know it has been incorporated in real designs, and
has generated several other projects here on Opencores. I even found it mentioned
in online research projects.


Instruction set: 8080
Data size: 8 bit
Address: 16 bit
Instruction: 8 bit
Language: Verilog
License: None (public domain)
Created under: Xilinx ISE, free webpack edition
Device: xc3c1000-4ft256
Slices: 1104
Slice flip flops: 296
4 input LUTs: 2082
Bonded IOBs: 33
GCLKs: 1

The CPU works entirely on positive clock edges and signals, but could be reconfigured
easily. It has wait state ability, and simple interrupt request/acknowledge structure.
The original 8080 method of fetching an external instruction to satisfy the interrupt is
preserved, and it is left up to an external interrupt controller to provide vectoring.

I have no problem with, and in fact encourage, commercial use, modifications (public
and private), etc.


2016/04/27 Status:

Fortunately or unfortunately I have been working with Verilog again, and have a few
changes and additions I want to make.

- Make it boot CP/M, probably up to 3.0. CP/M was the only real OS possibility for
the 8080, so stands to reason that would be a target.

- Reduce the gate count of the core (while perhaps making the code more clear).

I considered making it a MITS Altair 8800 emulator. It was kinda already headed
in that direction. This is both for nostalgia reasons as well as practical ones.
The MITS manuals are all online, it was a very popular machine, it was the first
real hobbyist computer, and I happen to have one in the garage gathering dust.
The problem is the the 88-DCDD, the one created by MITS itself, as well as many
other disk controllers of the era, directly read data off the disk. You kids
don't know what that means. It means you got a shift register, some logic to
sync the serial data to byte boundaries, and that was really about it. The CPU
would form a tight loop and read from the shift register and place in memory
as fast as possible, and that would be JUST enough to keep up with floppy disk
speeds (in fact the first floppy controller I used toggled the wait state line
to keep the CPU synced to the byte boundaries). Later on they came out with
buffered, fully controlled chips for floppies (Western digital).

It is possible to emulate such an interface, but at that point you would be emulating
timing as well. I notice that many MITS 8800 simulators attempt to do this, ie.,
emulating the exact timing of the 8080. The short answer is that I did my time
emulating existing systems like this, and it is a real time sink. There is nothing
in the CP/M bios that needs timing, its actually a very simple interface, I have
written several.

To host CP/M, the design needs two facillities that I didn't do the last time around.
The first is a flash drive interface, and the second, perhaps optional, is a DRAM
interface. I say perhaps optional because placing a 64kb memory block onchip is not
out of the question, and may actually be a good idea for small designs.

For the second point, reducing the size of the core, I am gratified that that became
sort of a contest here on Opencores. I think the winner is the 200 LUT design by
Ruiz & Moti. There should have been some kind of prize for what they accomplished.
It was probably far more work to make it that small than to make a "regular"
implementation. cpu8080 comes out at about 2000 LUTs. In my defense, this was
my first Verilog design, and I often looked at it and realized I could do better.


The CPU8080 project has passed a very complete CPU instruction test, and has run
a medium (but not large) piece of code, the SCS1 monitor, this morning. I have marked
the project as complete.

Tonight, after consideration, I think I will call it complete, at least for a while. I was
planning to take the design to a CP/M boot, but I think I have accomplished my
original purpose, and more. I have high confidence in this core, and I hope you all can
find uses for it. In the meantime, I have other projects, and my paid work calling.

Feel free to email me questions. Good luck, and good success with your projects.

2006/11/20 Status:

The SCS1 monitor/assembler signs on!

Here it is shown signing on, and executing a "dump 0 30" command to dump the first
30h bytes in the system.

The wires trailing off the XESS board are the Intronix USB analyzer wires.

Note that I added the sign on message to SCS1, normally it has no sign on.

This marks the first major piece of original 8080 software CPU8080 has run. I am
promoting the project status because of it.

2006/11/18 Status:

cpu8080 passes the Kelly Smith test, both in simulation and in hardware. There were
8 different cpu bugs solved by my count, so this is a very important series of updates.
Kelly Smith is an 8080 CPU test created in 1980 under the Microcosm Associates
brand name, and donated to the "SIG/M" CP/M user's group.

Its a very complete CPU test for all flags, modes and instructions, so passing that is
very good for the design.

Chris Strahm's modifications were incorporated, which include the following:

1. All constants that are not a single bit have their bit width specified. This was
required to remove Quartus errors.
2. Wait state ability is now optional. See cpu8080.v.
3. I/O instructions are now optional. See cpu8080.v.

The last two are part of the "super compact" core concept that Mr. Strahm is
following. See the section below for more details on this.

2006/11/15 Status:

The ADM 3A terminal emulation is very complete now. There are only a few modes
missing, reduced intensity and graphics. There are still a few issues with the
emulation, but they are minor, and should not impact any software.

Going forward, I have hooked up with Rich Cini's excellent Altair website and project
page at:

And the material there is really going to help me speed up this work.

I want to emphasize that I am not creating a "computer history" project here. The
logic is simple: The most complete test of a CPU is to run an extensive suite of
existing software, and that means existing operating systems, compilers and utilities,
of which the 8080 has quite a large supply. With the 8080 being more than 30 years
old, any such systems are going to look like a history project. The reason it's useful
to me is that a popular computer has a lot of preexisting software available for it.

In fact, Rich's site has already taken care of a large peice of work I had yet to do,
there is a full CPU test suite available there, 8080test.asm. The code is dated 1980,
and I'll bet the author never would have imagined it would be used to proof a new
implementation of the 8080. I'll post the result when that runs, which should be

Moving forward from there, the only piece of hardware left to emulate is the Altair
floppy disc controller, which looks pretty simple. After that, I will be able to use
Rich's rich catalog of disc images including CP/M 2.2, Microsoft Basic and others to
do a full 8080 checkout without so much as performing an assembly.

There is a Altera/Quartus version of the CPU being developed by a user who has been
emailing me of late. I hope to have more news on this later.

Previous status:

The design runs, abet with a simple program, on an XESS 1000 board. It prints
"Hello, FPGA world" on a VGA display. Here is a picture:

There have been a lot of improvements since the last version. First, I switched to the
50 mhz clkb, which gets divided down from the 100 XESS board clock. There are a
couple of reasons for this. The CPU core appeared to be deeply unhappy about running
at the top speed of the FPGA, and was showing internal failures. Second, the raw
100 mhz clock was coming direct from the oscillator, which I believe has a non-50/50
duty cycle. Since I have been using both edges, that's bad.

Second, I switched most clocking to positive edges. In fact, there is only one negedge
left, and that's because I haven't had time to test it.

Third, all of the read and write signals from the CPU, I/O and memory, were extended
by a cycle. This was required to get the single edge clocking going, and relaxes the
timing all around.

With these changes, the design is now running quite well. The "hello, FPGA world"
example now runs a terminal emulator loop, and the ADM 3A dumb terminal is fairly
complete. It features shift, caps, and control keys on input, and obeys the ADM 3A
controls, most of them, on output. See vgachr.v for details on what is and is not

By entering various characters in the terminal mode, I have tested all the usual
control characters, line up, down, left, right, clear screen, etc.

For anyone who has got far with trying this design out, I'll apologize in advance for
the character font. It was banged out in about 2 hours, I just wanted something
for test. I'll be cleaning it up later.

I'm currently using a Intronix 34 channel USB logic analyzer to verify the design on
hardware. Chipscope was just out of reach for me, it not only takes about $800 for
a full version, but requires you also to purchase the full, not free, version of ISE,
bringing the total cost to about $3000. I have all of the CPU signals brought out to
the analyzer, plus you'll notice an 8 bit "debug" bus that replaces the top 8 bits
of the address lines. This technique allows me to attach various signals to the "bus"
to be routed out to the external analyzer, and I can swap this to and from the debug
bus by modifying the pin assignments at the top level.

What's next is the Imsai monitor/assembler discussed below. I'm going to run that
under a simulator first, so that is 1 to 2 weeks off. I'll post a new picture when that

The testbench so far on the hardware consists of the following:

8080 core
ROM to store test program ("hello"/terminal emulator)
Select controller
Interrupt controller (no plans to use this on the hardware)
ADM 3A Dumb Terminal emulator

The wait state capability, as of this writing, has not been verified. For anyone curious,
the "select controller" has bits reserved for this, bits 0 and 1 of the mask register
will select from 0 to 3 wait states for that select.

I plan to add a bus hold (tristate) and acknowledge pins and mode, this will allow
connection of an external DMA. I don't plan to actually create a DMA, since this
project needs to end (da' wife is getting annoyed). I'll just activate the hold pin and
watch for high-z on all outputs.

I also plan to add a NMI (non maskable interrupt) pin. That will get a simple test
as well.

I placed an assembler file in the source that I will use for first tests with the core:

scs1.asm - An IMSAI monitor/assembler

This is a famous old program for the 8080. It preceeds CP/M. It's interesting
as first test because it only uses a single I/O port to the console.

Development systems

There is TONS of software available for the 8080. The best way to go about it is to run
a CP/M simulator on your host machine. Here are a few:

For development systems, try these forums:

This includes CP/M, assemblers, a basic compiler, the original Microsoft Basic interpreter,
Fortan compilers, Cobol, C (of course), Pascal, Modula, Algol, and Ada.

You can find a lot more with a simple search.

CP/M itself is a good, small operating system to run on your target if you wish. It can be
adapted to your target hardware with a very simple BIOS, which can run using a flash
memory as the "disk" for it. The entire system fits in less than 256kb (yes, actually less
than a meg), which was the common size of a floppy disk back when this CPU was

If you choose to run CP/M, the amount of software available is truly amazing. Try
these sections of the retroarchive:

CP/M was a popular system from the start of the home computer revolution to well
into the 1980's, and continues to have a following today.

I use a proprietary development system, the IP toolset, at my web site. This is not
meant as a plug for that system (the 8080 version is not even for sale), but simply to
explain why you will see a lot of the support files for the assembly code configured
for that system. There is nothing I have here that you cannot find for free at the
above sources. The main advantage I get from the IP toolset is that it runs natively
under Windows/XP.

CVS Format

The CVS repository is under cpu8080.

I'll apologize in advance, but repository is basically a dump of my Xilinx ISE directory. This
is not the clean way to do it, but it does have the advantage that if you are running
ISE, you can download the entire thing and just go. Here is a list of the important files
in the directory:

readme.txt - A copy of this text
cpu8080.txt - The documentation for the project, in plain ASCII.
cpu8080.v - The 8080 core
testbench.v - The testbench for the core. Also contains the peripherals for the core,
such as the peripheral select controller, the interrupt controller, the test ROM, RAM, and
anything else required.
vgachr.v - The ADM 3A dumb terminal emulator, keyboard interface, and MITS Serial
I/O emulator.
vga.vhd - The stripped XESS vga timing generator/pixel shift register.
ps2_kbd.vhd - The XESS keyboard interface.

The other files are the testbench running files, like the stimulus package. I don't even
know what half of them are, sorry, I only started using the system 2 weeks ago!

Shameless plug

For people who want ask me questions, or find out more about what I am doing, my
information is:

Web page:

Disclaimer: The above web page does include commercial content, ads, rants, etc.


Here are some locations that have the original 8080 documentation:

That last link contains the "8080 Assembly language programming manual", which is the
book that I used to construct cpu8080, from my original coffee stained edition, bought in

For people interested in the difference between the 8080 and its predecessor, the 8008,
the following site is available:

You can find the User's reference manual for the ADM 3A dumb terminal, which was used
to produce the emulation used in this design, at:

You can find a copy of the manual for the REALLY elementary MITS Serial I/O card used
to construct the serial port emulation on the design at:

The super compact core

Chris Strahm has been working on a "super compact" 8080 core. The idea is to strip out
features that are not absolutely required for most designs.

He's been reporting cell counts (LUTS) of below 1500.

© copyright 1999-2016, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.