Cpu Generator :: Overview
Project maintainers
Details
Name: cpugen
Created: Sep 3, 2003
Updated: Dec 20, 2009
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View
Other project properties
Category: Processor
Language: VHDL
Development status: Stable
Additional info:
none
WishBone Compliant: No
License:
Description
Cpugen (TM) generates customizable RISC cpu cores.
It allows direct customization of address/data/instruction bus size,
interrupt handling, indirect addressing, data/instruction latency
timings and custom instructions definition.
It is targeted to low size FPGAs, easy to use and getting started with.
GNU VHDL source code provided.
Features
1) Portability:
vendor dependent blocks (ex. memory blocks) are kept separate from vendor independent logic.
Customizable built-in assembler with data/instruction memory files generation; output file formats for the following environments:
- Altera
- Xilinx
- binary
- testbench
2) Configurability:
In order to optimize logic resources and take advantage of FPGA flexibility; targeted to low size FPGAs; it permits to define:
- address/data/instruction bus size
- stack type/depth
- interrupt
- indirect address
- data/instruction variable latency
- custom instructions support
3) Graphical user interface:
4) Easy to use and getting started with: - Tutorial and example files are supplied with the package - Xilinx/Altera 4/8/16/32 bit cpu applications samples - GNU VHDL source code