OpenCores

de1_olpcl2294_system :: Overview

Project maintainers

Details

Name: de1_olpcl2294_system
Created: Nov 18, 2009
Updated: Apr 6, 2010
SVN Updated: Mar 29, 2011
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Prototype board
Language: Verilog
Development status: Alpha
Additional info: none
WishBone compliant: Yes
WishBone version: n/a
License: LGPL

Description

This project uses two off the shelf boards and interfaces them. The processor board used is a Olimex LPC-L2294 and the FPGA board is a Terasic DE1. A Olimex ARM-USB-OCD was used to load and debug the code. The boards were cabled together with floppy and hard drive cables. The entire setup cost less than $350.

The bridge from the wb_async_mem_bridge project is used to interface the External Memory Controller to the Wishbone bus on the FPGA. Currently the SRAM, GPIOs & HEX LED display is connected and there are plans to add the other interfaces on the DE1 as time permits.

Ecos has been ported and there are some simple examples of multithreading and interrupts. The shell interface was borrowed from redboot has been striped down and adapted to run in it's own thread.


http://www.olimex.com/dev/lpc-l2294.html
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=83
http://www.olimex.com/dev/arm-usb-ocd.html

© copyright 1999-2017 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.