DS1621 model
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Details
Name: ds1621
Created: Dec 17, 2009
Updated: Dec 20, 2009
SVN Updated: Apr 7, 2010
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: Dec 17, 2009
Updated: Dec 20, 2009
SVN Updated: Apr 7, 2010
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties
Category:Testing / Verification
Language:Verilog
Development status:Beta
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:Verilog
Development status:Beta
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
DS1621 verilog model with testing tasks. Testing elements assume the existence of the low level write/read (need to be written by the user) and include the macro tasks based on that write/read tasks. A test with macros is included. Only the Slope and the Counter registers are not supported.
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