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DDR2 mem controller for Digilent Genesys Board :: Overview

Project maintainers

Details

Name: genesys_ddr2
Created: May 3, 2013
Updated: May 6, 2013
SVN Updated: May 8, 2013
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Memory core
Language: Verilog
Development status: Beta
Additional info: FPGA proven
WishBone compliant: Yes
WishBone version: n/a
License: LGPL

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