HyperTransport Tunnel :: Overview
Other project properties
A HyperTransport Tunnel controller written in SystemC. HyperTransport (HT) is a high-performance chip-to-chip interconnect architecture. A tunnel has two HT ports to allow it to be used inside a chain of components. More information about HyperTransport can be found at the HyperTransport Consortium web site.
- Written in synthesisable SystemC
- Designed with the HyperTransport 2.0b specification
- Core configurable options include:
- Retry mode
- In-vc packet reordering
- Extendable configuration register space
- Buffer size
- Either internal or external deserializer data alignment
- 2, 4 or 8-bit link support
- Platform independent
- Throughput of 32 x Core Frequency bits/s (An FPGA running at 100 Mhz could have an 8-bit link at 400 MT/s, an FPGA running at 75 Mhz could have a 4-bit link at 600 MT/s or an ASIC running at 250Mhz could have an 8-bit link running at 1000 MT/s)
- High level documentation currently being worked on
- Complete, but not prototyped
- There are many testbenches, most of them are self-checking but others only produce output that must be manually inspected. The testbenches were designed to quickly validate the design, not for full coverage of limit cases.
This project was done at l'École Polytechnique de Montréal in the microelectronic research group (Groupe de recherche en microélectronique - GRM) by Ami Castonguay and Yvon Savaria, in collaboration with Bernard Racine, Jean-François Bélanger and many others. Financial support was provided by the National Sciences and Engineering Research Council of Canada. Tools support was provided by CMC Microsystems.