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I2C Slave :: Overview

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Details

Name: i2cslave
Created: Nov 7, 2008
Updated: Jul 2, 2017
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Communication controller
Language: Verilog
Development status: Stable
Additional info: Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: GPL

Description

i2cSlave is a minimalist I2C slave IP core that provides the basic framework for the implementation of custom I2C slave devices. The core provides a means to read and write up to 256 8-bit registers. These registers can be connected to the users custom logic, thus implementing a simple control and status interface.

A full Icarus Verilog test bench is available.

Test it for yourself, using the free Icarus Verilog simulator and the free GTKWave wave form viewer. Only 6 simple steps!
- Download and install Icarus Verilog.
- Download and install GTKWave.
- Download the project files.
- Execute sim/build_icarus.bat and sim/run_icarus.bat
- Execute sim/viewWave.bat and check out the results.
- In GTKWave, use "Search >> Signal Search Tree" to view more waves.

Features

- Standalone. No microprocessor required.
- Create your own custom I2C peripheral.
- Only 143 macrocells in CPLD.
- I2C bus speeds of 100Kbps and 400Kbps.
- Easily configurable for different input clock frequencies.
- Full Icarus Verilog test bench.

Status

- Tested in FPGA
- Tested in simulation

News

Now available, Altera Quartus project for Base2Designs FPGA-DEV-KIT and test software for the Aardvark I2C Host Adapter. Download the latest project files now.

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