部分翻译
News
| Nov 25, 2009 |
There is new fix coming soon, which will provide properly reading data from device while ports configured as output. |
| Nov 22, 2009 |
Updated svn with assignments fixes. Code contains a lot of junk entities and useless stuff - it's all for the future or just my old thoughts. |
| Nov 22, 2009 |
Updated description. |
| Nov 22, 2009 |
I'll upload entire Xilinx project soon. |
| Nov 21, 2009 |
Uploaded svn. There are only two files now: device and testbench. Supports only 0 mode for Group A and Group B. All signals same as in real device(inverted too). Warning: 'data' must be provided before nWR will be placed on the pin in write mode. |
| Nov 21, 2009 |
Updated Description with link to datasheets site. |
| Nov 17, 2009 |
And excuse me for word 'realisation' with s instead of z)))) |
| Nov 17, 2009 |
All operations are triggered by the nRD or nWR, when nCS comes to the pin. |
| Nov 17, 2009 |
I'm very busy last time)). Pair lines of code nested on my PC. I 'll upload ones around week. Status: realisation of Group A port A completed. |
© copyright 1999-2012
OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.