Lattice 6502 :: Overview

Project maintainers


Name: lattice6502
Created: Oct 13, 2010
Updated: Dec 17, 2010
SVN Updated: Dec 14, 2010
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Processor
Language: VHDL
Development status: Beta
Additional info: FPGA proven
WishBone Compliant: No
License: LGPL


This document describes my implementation of a 6502 microprocessor into a Lattice LCMXO2280C FPGA. The hardware is based on an existing PCB leftover from a controller for a soft X-ray generator. It is anticipated that the design can be ported to other FPGA devices. It is written in VHDL and used GNU ghdl for initial development and Lattice ispLeaver to implement the design into the FPGA. The GNU software was found to be significantly faster than Lattice. Files and information is provided to implement the design into both Lattice parts and hopefully other parts.

The 65C02 instructions have yet to be implemented. The timing bears no relationship with that of a genuine 6502; it is intended to execute the instruction set as fast as possible. This will make it very difficult to use on an Apple 2 or other 6502 based PC.

Also included are a UART TX and RX and sufficient assembly language firmware to communicate to a dumb terminal (IE Linux gtkterm). This provides a simple OS, Kernel or monitor that is able to display and modify memory and load Motorola S code. This monitor is burnt into the FPGAs ROM. The capability to load and execute a program via the terminal is much faster than re-generating the FPGA each time a program change is required to validate an instruction.

The status is such that code can be run on a programmed FPGA and instructions verified one by one. I intend to provide two zip files, one with minimum necessary to implement a FPGA and one with all my modules.

© copyright 1999-2017, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.