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Leros: A Tiny Microcontroller for FPGAs :: Overview

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Details

Name: leros
Created: Sep 5, 2011
Updated: Mar 6, 2012
SVN Updated: Nov 8, 2012
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Processor
Language: VHDL
Development status: Stable
Additional info: Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: BSD

Description

Leros is a 16-bit processor optimized for FPGAs. It consumes less than 200 logic cells and 1-2 on-chip memories.
Leros is programmed in assembler and in a restricted subset of Java. Leros is a direct competitor to tiny processor
cores, such as PicoBlaze.

Comparison with PicoBlaze

Leros targets the same application area as PicoBlaze and
is about the same size. Following list gives the main differences:

* Truly open source (BSD)
* Compiles on Altera and Xilinx tools
* Leros is a 16 bit architectures instead of 8 bit
* Leros has no restrictions on code and data size
* Single clock cycle instructions
* Java based assembler is platform independent
* Simplified Java compiler for Leros available

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